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Current Flattening in Software and Hardware for Security Applications

Current Flattening in Software and Hardware for Security Applications. Authors: R. Muresan, C. Gebotys Presentation By: Radu Muresan. Outline. Introduction Power analysis attacks (PAAs) Definitions, examples, countermeasures Current flattening technique

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Current Flattening in Software and Hardware for Security Applications

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  1. Current Flattening in Software and Hardware for Security Applications Authors: R. Muresan, C. Gebotys Presentation By: Radu Muresan CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  2. Outline • Introduction • Power analysis attacks (PAAs) • Definitions, examples, countermeasures • Current flattening technique • Definition, methodology, implementations • Current flattening as a countermeasure against PAAs • Results and conclusions CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  3. Plaintext Ciphertext Encryption Message Channel ke Plaintext Decryption Key Channel kd Key Generation Introduction • Embedded systems are increasingly used in security applications • The software and the hardware components must be secure against all threats • Current flattening is a potential countermeasure against PAAs Secret-key Cryptosystem: ke = kd Public – key Cryptosystem: ke ≠ kd CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  4. Power Supply Current or Power Measurement R Attacker’s Point Cryptographic Device What is a Power Analysis Attack ? • Side-channel attacks exploit correlation between secret parameters and variations in timing, power consumption, and other emanations from cryptographic devices to reveal secret keys CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  5. Example, DPA Attack on a Scalar Multiplication Algorithm for EC Protocols • DPA, uses correlation between power consumption and specific key-dependent bits • kP, scalar multiplication • Double-and-add approach, binary k(2) = (kn-1,...,k0) • kP1,kP2,...,kPn => Ci(t) = power • kn-1 = 1; After the first iteration => Q[0] = 2Pi • Second iteration • If kn-2=1 => Q[1] = 4P • If kn-2=0 => Q[1] = 5P • g(t)=<Ci(t)>i=1,...,k|si=1 - <Ci(t)>i=1,...,k|si=0 CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  6. Example, DPA Attack on a Scalar Multiplication Algorithm for EC Protocols Simulated correlation function between the points 4Pi and power consumption Ci(t) when kn-2 = 0. • A peak is observed when 4Pi are computed by the card • No peak is observed when 4Pi are never computed by the card CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  7. Countermeasures Against PAAs • Against timing attacks • Equalizing; Randomizing; Blinding • Against simple power analysis attacks • Avoiding; Creating; Symmetric • Against differential power analysis attacks • Randomization; Blinding • Hardware: non-deterministic techniques • Against all PAAs • Proposed: current flattening technique CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  8. Attacker’s Point Cryptographic Device External Current Filtering Devices Current Flattening (internal) What is Current Flattening? • Current flattening targets a flat (emission free) current consumption measured at an attacker’s point of a cryptographic device CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  9. Behind Current Flattening • Current consumption in a processor is a function of: • The hardware architecture • The instruction type • The instruction sequencing • Data manipulated Examples of current dynamics CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  10. Software Method • Program execution is composed of two types of cycles • charging; discharging • Code transformations are generated for classes of instructions Example Current measurements used for determining code transformations CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  11. Hardware Method • Pipeline current flattening module CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  12. Hardware Method • Feedback current module CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  13. Does Current Flattening Protect Against PAAs? • Software method does not support DPA due to the fact that the program to data dependencies are not covered • Hardware method has potential to cover all PAAs • Supports real-time current adjustment at the clock frequency • Covers both current to data and to instruction dependencies CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  14. Results of Software Flattening • The experiments used the polymulNIST.asm implementation of an EC scalar multiplication (kP), where: • P a fixed point on a known elliptic curve • k a secret key • Target processor: Motorola SC140 DSP Real current measurements CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  15. Pk-Pk current variation reduced by 70 to 78% Energy consumption increased by 71 to 74% Execution time increased by up to 135% Results of Software Flattening Data analysis for software flattening CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  16. Results of Hardware Flattening • Instantaneous current simulation for polymul.asm • polymul.asm is a subroutine of polymulNIST.asm • polymul.asm is a target of PAAs • Target system • Motorola SC140 DSP plus the Feedback Current Module Current simulation and real current measurement CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  17. Pk-Pk current variation reduced by 94 to 97% Energy consumption increased by up to 16% Execution time increased by up to 29% Results of Hardware Flattening Data analysis for hardware flattening CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  18. Conclusions • The paper presented the mechanisms of the internal current flattening technique (ICF) • ICF controls power consumption and current variation • Countermeasure against PAAs • Limitations • Increased execution time and energy consumption CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  19. Future Work • Investigate an ASIC implementation of the PAAR architecture • Methods to improve the performance and energy consumption of implementations using ICF CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  20. References Used for the Presentation • Slides 3 and 4 • W. Mao, “Modern Cryptography”, Prentice Hall, 2004 • O. Kommerling, M. G. Kuhn, “Design principles for tamper-resistant smartcard processors”, In Workshop on Smartcard Technology 1999 • Slides 5, 6 and 7 • J-S. Coron, “Resistance against dpa for elliptic curve cryptosystems”, CHES’99 • P. Kocher, et al., “Differential power analysis”, In CRYPTO’99 • Slide 9 • R. Muresan, C. Gebotys, “Instantaneous current modeling in a complex vliw processor core”, In ACM TECS, 2004 CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

  21. THANK YOU! Questions? CODES+ISSS'04, September 8-10, 2004, Stockholm, Sweden

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