TSS@ETS10 Logic Simulation
TSS@ETS10 Logic Simulation. Vishwani D. Agrawal Department of ECE, Auburn University Auburn, AL 36849, USA www.ece.auburn.edu/~vagrawal vagrawal@eng.auburn.edu Prague, May 22, 2010, 2:30-6:30PM. Logic Simulation. What is simulation? Design verification Circuit modeling
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