140 likes | 244 Views
Scalable Pattern Matching for High Speed Networks. Authors : Christopher R.Clark and David E. Schemmel Publisher : Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM) Present: Kia-Tso Chang Date: November 1 2007. Three designed method on FPGA.
E N D
Scalable Pattern Matching for High Speed Networks Authors: Christopher R.Clark and David E. Schemmel Publisher: Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM) Present: Kia-Tso Chang Date: November 1 2007
Three designed method on FPGA • 1. brute-force, • 2. deterministic finite automata (DFA) • 3. non-deterministic finite automata (NFA).
Upper bound of per matcher • Each FPGA logic element (LE) can implement up to a four-input logic gate and a flip-flop,