FPGA based High speed and low area cost pattern matching

1. FPGA based High speed and low area cost pattern matching Authors: Jian Huang, Zongkai Yang, Xu Du, and Wei Liu Publisher: Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM) Present: Kia-Tso Chang Date: Jan 22 2008 1

2. outline • Introduction • Half-byte comparators (HBC) • Architecture of pattern matching • Evaluation

3. Introduction • byte comparator does not fit the 4-input LUT in FPGA . • Large numbers of fan out of input signals will cause the decrease of system operating frequency. • The amount of comparators will increase with the number of pattern of system.

4. Half-byte comparators (HBC) • HBCs are simply 4 to 1 decoders. If the input 4 bits match the value configured in the HBC, the output of HBC will be asserted high. A HBC just fits an FPGA LUT .

5. Architecture of pattern matching

6. Architecture of pattern matching 6

7. Architecture of pattern matching

8. Architecture of pattern matching

9. Evaluation

10. Evaluation

11. Evaluation