1 / 32

Boolean derivatives

Boolean derivatives. Given:. Calculation of the Boolean derivative:. Derivatives for complex functions. Boolean derivative for a complex function: Example:. Additional condition:. Boolean differentials and fault diagnosis. Correct output signal :. x 1 = 0 x 2 = 1 x 3 = 1 dy = 0.

sheri
Download Presentation

Boolean derivatives

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Boolean derivatives Given: Calculation of the Boolean derivative:

  2. Derivatives for complex functions Boolean derivative for a complex function: Example: Additional condition:

  3. Boolean differentials and fault diagnosis Correct output signal: x1 = 0 x2 = 1 x3 = 1 dy = 0 x1 = 0 x2 = 0 x3 = 0 dy = 1 Erroneous output signal:

  4. Boolean differentials and fault diagnosis Rule: Diagnosis: = 0 The linex3works correct There is a fault: The fault is missing

  5. Binary Decision Diagrams Functional synthesis BDDs: Shannon’s Theorem: Example: Using the Theorem for BDD synthesis: y x1 x2 xk y x3 x3 x4 x4

  6. Binary Decision Diagrams Elementary BDDs S D Flip-Flop J JK Flip-Flop q c D q D C S C K q’ c q’ R K R RS Flip-Flop q’ J q c S S R C q’ q’ U R R U - unknown value

  7. Building a SSBDD for a Circuit Structurally Synthesized BDDs: DD-library: y a b Given circuit: x1 x1 x22 a a b x21 1 x2 y x21 x3 & x22 1 SSBDD x3 Superposition of DDs b y x22 x22 a y x1 Compare to x3 x3 Superposition of Boolean functions: x21 b a

  8. High-Level DDs for Finite State Machines State Transition Diagram: DD:

  9. High-Level Decision Diagrams R Superposition of High-Level DDs: A single DD for a subcircuit 2 0 y # 0 4 1 R 2 M1 0 0 2 y y R + R 3 1 1 2 R2 1 IN + R 2 1 IN 2 R 1 3 0 y R * R 2 R2 +M3 1 2 1 IN* R 2 M2 Instead of simulating all the components in the circuit, only a single path in the DD should be traced

  10. I1: MVI A,D A  IN I2: MOV R,A R  A I3: MOV M,R OUT  R I4: MOV M,A OUT  A I5: MOV R,M R  IN I6: MOV A,M A  IN I7: ADD R A  A + R I8: ORA R A  A  R I9: ANA R A  A  R I10: CMA A,D A  A Decision Diagrams for Microprocessors High-Level DDs for a microprocessor (example): DD-model of the microprocessor: Instruction set: 1,6 A I IN 3 2,3,4,5 I R OUT A 4 7 A + R A 8 2 A  R I A R 9 A  R 5 IN 10  A 1,3,4,6-10 R

  11. Mapping Transistor Faults to Logic Level Function: Faulty function: Generic function with defect: y x1 x4 Short Test calculation by Boolean derivative: x2 x5 x3

  12. Functional Fault Model Bridging fault causes a feedback loop: Example: A short between leads xkand xlchanges the combinational circuit into sequential one x1 y & x2 & x3 Equivalent faulty circuit: x1 y & & x2 x3 tx1 x2 x3 y 1 0 1 0 2 1 1 1 1 Sequential constraints: &

  13. & & & Structural Test Generation • Fault sensitisation: • x7,1= D • Fault propagation: • x2=1, x1=1, b =1, c =1 • Line justification: • x7= D = 0: x3= 1, x4= 1 • b = 1: (already justified) • c = 1: (already justified) Structural gate-level testing: Path activation 1 1 Macro 1 d 1 1 a & 2 & 71 D D D 1 & e 3 7 72 b 1 1 4 y D D & 5 73 c 1 6 Test pattern Symbolic fault modeling: D = 0 - if fault is missing D = 1 - if fault is present

  14. Example: Test Generation with SSBDDs Testing Stuck-at-1 faults on paths: y x21 x11 1 x11 x1 x21 & x2 x31 x4 x12 x12 1 x31 x3 y & 1 x4 x22 x32 x13 1 Test pattern: & x13 x1 x2 x3 x4 y 10010 & x22 0 x32 Tested faults: x211, x311, x130

  15. Example: Test Generation with BDDs Testing Stuck-at faults on inputs: y x21 x11 x11 x1 x21 SSBDD: & x2 x31 x4 x12 x12 x31 x3 y & 1 x22 x32 x4 x13 & x13 y x2 x1 1 & x22 BDD: x32 x1 x2 x3 x4 y D10-D x4 x3 Test pair D=0,1: x2 0 Tested faults: x10, x11

  16. Test generation Test generation by using disjunctive normal forms

  17. Multiple Fault Testing Testing multiple faults by pairs of patterns To test a path under condition of multiple faults, two pattern test is needed As the result, either the faults on the path under test are detected or the masking fault is detected Example: The lower path from b to output is under test A pair of patterns is applied on b There is a masking fault c 1 1st pattern: fault on b is masked 2nd pattern: fault on c is detected 11 10 a & 01 b 11 & 1 faults 01 (00) & 01 & 00 (11) 10 (11) c & 11 d 11(00) • The possible results: • 01 - No faults detected • 00 - Either b 0or c 1detected • 11 - The fault b 1isdetected

  18. Delay Faults Delay fault activated, but not detected Two models: - gate delay - path delay Test pattern pairs: The first test initializes the circuit, and the second pattern sensitizes the fault Robust delay test: If and only if when L is faulty and a test pair is applied, the fault is detected independently of the delays along the path x1 1x0 B 11 & 1 D 1xxx0 & A y x2 C & 01 & 0xxxx1 x3 11 Robust delay test x1 11 B 00 0xxxxx1 & D y 0xxx1 & A x2 C & 10 & 1xxxx0 x3 11

  19. I1: MVI A,D A  IN I2: MOV R,A R  A I3: MOV M,R OUT  R I4: MOV M,A OUT  IA I5: MOV R,M R  IN I6: MOV A,M A  IN I7: ADD R A  A + R I8: ORA R A  A  R I9: ANA R A  A  R I10: CMA A,D A  A Test Generation Test program generation for a microprocessor (example): DD-model of the microprocessor: Instruction set: 1,6 A I IN 3 2,3,4,5 I R OUT IN 4 7 A + R A 8 2 A  R I A R 9 A  R 5 IN 10  A 1,3,4,6-10 R

  20. Test Generation Test program generation for a microprocessor (example): DD-model of the microprocessor: Scanning test for adder: Instruction sequence I5 I1 I7 I4 for all needed pairs of (A,R) 1,6 A I IN I4 3 OUT 2,3,4,5 I R OUT IN I7 A 4 7 A + R I1 A A 8 R IN(2) 2 A  R I A R I5 R 9 A  R 5 IN(1) IN Time: 10 t t - 1 t - 2 t - 3  A 1,3,4,6-10 Observation Test Load R

  21. Test Generation Test program generation for a microprocessor (example): Conformity test for decoder: Instruction sequence I5 I1 DI4 for all DI1 -I10 at given A,R,IN DD-model of the microprocessor: 1,6 A I IN Data generation: 3 2,3,4,5 I R OUT IN 4 7 A + R A 8 2 A  R I A R 9 A  R 5 IN 10  A 1,3,4,6-10 Data IN,A,R are generated so that the values of all functions were different R

  22. Deductive Fault Simulation Gate-level fault list propagation Fault list calculation: 1 1 La = L4 L5 Lb = L1 L2 Lc = L3  La Ly = Lb- Lc ----------------------------------------------------------- Ly = (L1 L2) - (L3 (L4 L5)) b & 1 1 2 Library of formulas for gates 1 1 y 0 0 3 & 0 0 c 4 1 0 a 5 La– faults causing erroneous signal on the node a Ly – faults causing erroneous signal on the output node y

  23. Deductive Fault Simulation Macro-level fault propagation: Fault list calculated: 1 1 b & Ly = (L1 L2) - (L3 (L4 L5)) 1 1 2 1 1 y 0 0 3 & 0 0 c 4 1 0 a 5 Solving Boolean differential equation: Lk

  24. Critical Path Tracing Problems: 1 1 1 b & & 1 1 1 2 0/1 1 1 1 y y 1/0 0 0 1 3 & & 0 0 c 4 1 1 0 a 5 The critical path is not continuous y 1 1 2 & 0 1 1 y 1/0 3 4 & 1 1 5 The critical path breaks on the fan-out

  25. Parallel Critical Path Tracing • Handling of fanout points: • Fault simulation • Boolean differential calculus 1011 x1 & 1110 x2 1011 1 y 1001 x3 x1 F x2 y x xk Detected faults vector: - 10 - T1: No faults detected T2: x1 1 detected T3: x1 0 detected T4: No faults detected

  26. F F F F F F F 1 2 3 4 5 6 7 T 0 1 1 0 0 0 0 1 T 1 0 0 1 0 0 0 2 T 1 1 0 1 0 1 0 3 T 0 1 0 0 1 0 0 4 T 0 0 1 5 Combinational Fault diagnosis Fault localization by fault tables 0 1 1 0 T 0 0 1 0 0 1 1 6 Fault F located 5 Faults F and F are not distinguishable 1 4 No match, diagnosis not possible

  27. Combinational Fault Diagnosis Minimization of diagnostic data • To reduce the cost of building a fault table, the detected faults may be dropped from simulation • All the faults detected for the first time by the same vector produce the same column vector in the table, and will included in the same equivalence class of faults • Testing can stop after the first failing test, no information from the following tests can be used With fault dropping, only 19 faults need to be simulated compared to the all 42 faults The following faults remain not distinguishable: {F2, F3}, {F1, F4}. A tradeoff between computing time and diagnostic resolution can be achieved by dropping faults after k >1 detections

  28. Method: F1 mayinfluence both outputs, F2 mayinfluence only x8 A test pattern 0010 activates F1 up to the both outputs, and F2 only to x8 If both outputs will be wrong, F1 is present, and if only x8 will be wrong, F2 is present 0 x 1 x 1 0 7 x 2 1 x x 5 1 3,1 x x 1 8 3 x x 3,2 6 & x 4 0 Improving Diagnostic Resolution Generating tests to distinguish faults Faults are influencing on different outputs: F1:x3,1  0 F2: x4  1

  29. Method: Both faults influence the same output of the circuit One of them should be blocked Two possibilities: A test pattern 0100 activates the fault F2. F1 is not activated: the line x3,2 has the same value as it would have if F1 were present A test pattern 0110 activates the fault F2. F1 is now activated at his site but not propagated through the AND gate 0 x 1 x 1 1 7 x x x 2 5 5,1 1 x 5,2 x 0/1 3,1 x x 1 x 8 3 x 3,2 6 & x 4 0 Improving Diagnostic Resolution Generating tests to distinguish faults How to activate a fault without activating another one? F1:x3,2  0F2: x5,2  1

  30. Sequential Fault Diagnosis Sequential fault diagnosis by Edge-Pin Testing Diagnostic tree: • Two faults F1,F4remain indistinguishable • Not all test patterns used in the fault table are needed • Different faults need for identifying test sequences with different lengths • The shortest test contains two patterns, • the longest four patterns

  31. Sequential Fault Diagnosis Guided-probe testing at the gate level Searh tree: Faulty circuit

  32. & & & Sequential Fault Diagnosis Guided-probe testing at the macro-level • Rules on DDs: • Only the nodes where the leaving direction coincides with the leaving direction from the DD should be pinponted • If simulation shows that these nodes cannot explain the faulty behavior they can be dropped There is a fault on the line 71 1 Macro 1 d a & 2 1 & 71 0 1 0 & e 3 7 72 y b 1 4 y 73 6 1 0 & 5 1 73 1 c 1 0 6 5 1 Nodes to be pinpointed: Gate level: c, e, d, 1, a, 71 (6 attempts) Macro level (DD): 1, 71 (2 attempts) 71 72 2 0

More Related