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Exploring a CPLD/FPGA-based Triggering System for LCLS

Exploring a CPLD/FPGA-based Triggering System for LCLS. Matthew T. Brown Office of Science, Science Undergraduate Laboratory Internship Program Advisor: Ron Akre. CPLD/FPGA Basics. Gates Macrocells LUTs JTAG Programmer Xilinx ISE. Xilinx Cool Runner XPLA XCR3064XL.

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Exploring a CPLD/FPGA-based Triggering System for LCLS

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  1. Exploring a CPLD/FPGA-based Triggering System for LCLS Matthew T. Brown Office of Science, Science Undergraduate Laboratory Internship Program Advisor: Ron Akre

  2. CPLD/FPGA Basics • Gates • Macrocells • LUTs • JTAG Programmer • Xilinx ISE

  3. Xilinx Cool Runner XPLA XCR3064XL

  4. Xilinx Spartan 3 XC3S200PQ208-5

  5. The Task at Hand • 360Hz fiducial signal • Set delays • Triggering requirements • Delay • Pulse length • Jitter

  6. How It’s Done • 24-bit counter • Comparators • Flip flops • Design entry • Schematic • Text (VHDL code written for 8 channels)

  7. Simple Timing Diagram

  8. Schematic Example

  9. CPLD Results Not good enough!

  10. FPGA Results

  11. FPGA Results Strike Back • Jitter measured to be below 2 picoseconds

  12. Return of the FPGA Results • Onboard Arcturus Coldfire Processor • Four DCMs on the chip allow for sub-clock cycle phase adjusting for the triggers

  13. Conclusion and Possible Future Work • CPLD = No • FPGA = Yes • Need to: • Build a board with all 8 channels on it • Complete the computer-FPGA interface

  14. Acknowledgements • Thanks to Ron Akre, Jeff Olsen, Bo Hong, and Anatoly Krasnykh for help on this project. • Thanks to Steve Rock, Susan Schultz, and Farah Rahbar for managing us kids and the SULI program at SLAC. • Questions? • Sources: • http://supercomputing.fnal.gov/slac_logo.jpg • http://images.amazon.com/images/P/6305428387.01.LZZZZZZZ.jpg • http://therawfeed.com/pix/this_is_sparta.jpg

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