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Computer Architecture: A Constructive Approach Sequential Circuits Arvind

Computer Architecture: A Constructive Approach Sequential Circuits Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology Revised February 21, 2012 ( Slides from # 16 onwards). OpSelect - Add, Sub, ... - And, Or, Xor, Not, ...

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Computer Architecture: A Constructive Approach Sequential Circuits Arvind

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  1. Computer Architecture: A Constructive Approach Sequential Circuits Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology Revised February 21, 2012 (Slides from #16 onwards) http://csg.csail.mit.edu/6.S078

  2. OpSelect - Add, Sub, ... - And, Or, Xor, Not, ... - GT, LT, EQ, Zero, ... Sel Sel lg(n) lg(n) O0 O1 On-1 O0 O1 On-1 A0 A1 An-1 A O A Result A Demux Decoder ALU Mux lg(n) Comp? . . . B . . . . . . Combinational circuits Such circuits have no cycles (feedback) or state http://csg.csail.mit.edu/6.S078

  3. A simple synchronous state element Edge-Triggered Flip-flop D Q ff C C D Q Metastability Data is sampled at the rising edge of the clock http://csg.csail.mit.edu/6.S078

  4. EN D Q ff C C EN D Q Flip-flops with Write Enables D Q ff EN C dangerous! EN 0 1 Q D C ff Data is captured only if EN is on http://csg.csail.mit.edu/6.S078

  5. D D D D D D D D En ff ff ff ff ff ff ff ff C Q Q Q Q Q Q Q Q Registers Register: A group of flip-flops with a common clock and enable Register file: A group of registers with a common clock, input and output port(s) http://csg.csail.mit.edu/6.S078

  6. Clock WE ReadSel1 ReadData1 Register file 2R + 1W ReadSel2 ReadData2 WriteSel WriteData RSel1 WSel WData C RData1 register 0 RSel2 WE register 1 RData2 Register Files No timing issues in reading a selected register http://csg.csail.mit.edu/6.S078

  7. WE ReadSel1 ReadData1 Register file 2R + 1W ReadSel2 ReadData2 WriteSel WriteData WE ReadSel ReadData Register file 1R + 1R/W R/WSel R/WData Register Files and Ports Ports were expensive multiplex a port for read & write http://csg.csail.mit.edu/6.S078

  8. We can build useful and compact circuits using registers Example: Multiplication by repeated addition http://csg.csail.mit.edu/6.S078

  9. Multiplication by repeated addition a0 m0 b Multiplicand a Muliplier * 1101 (13) 1011 (11) 1101 + 1101 + 0000 + 1101 10001111 (143) a1 m1 0 add4 a2 m2 add4 a3 m3 mi = (a[i]==0)? 0 : b; add4 http://csg.csail.mit.edu/6.S078

  10. Combinational 32-bit multiply function Bit#(64) mul32(Bit#(32) a, Bit#(32) b); Bit#(32) prod = 0; Bit#(32) tp = 0;for(Integer i = 0; i < 32; i = i+1)begin     Bit#(32) m = (a[i]==0)? 0 : b;     Bit#(33) sum = add32(m,tp,0);     prod[i] = sum[0];tp = truncateLSB(sum); endreturn {tp,prod};endfunction http://csg.csail.mit.edu/6.S078

  11. Design issues with combinational multiply • Lot of hardware • 32-bit multiply uses 31 addN circuits • Long chains of gates • 32-bit ripple carry adder has a 31 long chain of gates • 32-bit multiply has 31 ripple carry adders in sequence! The speed of a combinational circuit is determined by its longest input-to-output path http://csg.csail.mit.edu/6.S078

  12. Expressing a loop using registers function Bit#(64) mul32(Bit#(32) a, Bit#(32) b); Bit#(32) prod = 0; Bit#(32) tp = 0;for(Integer i = 0; i < 32; i = i+1)begin     Bit#(32) m = (a[i]==0)? 0 : b;     Bit#(33) sum = add32(m,tp,0);     prod[i] = sum[0];tp = truncateLSB(sum); endreturn {tp,prod};endfunction Need registers to hold a, b, tp prod and i Update the registers every cycle until we are done http://csg.csail.mit.edu/6.S078

  13. Expressing a loop using registers for(Integer i = 0; i < 32; i = i+1)begin     let s = f(s);      endreturn s; s0 f +1 s i (init 0) <32 http://csg.csail.mit.edu/6.S078

  14. Sequential multiply Reg#(Bit#(32)) a <- mkRegU(); Reg#(Bit#(32)) b <- mkRegU(); Reg#(Bit#(32)) prod <-mkRegU();Reg#(Bit#(32)) tp <- mkRegU(); Reg#(Bit#(6)) i <- mkReg(32); rule mulStep if (i < 32);     Bit#(32) m = (a[i]==0)? 0 : b;     Bit#(33) sum = add32(m,tp,0);     prod[i] <= sum[0];tp <= sum[32:1]; i <= i+1;endrule state elements a rule to describe dynamic behavior So that the rule won’t fire until i is set to some other value http://csg.csail.mit.edu/6.S078

  15. Dynamic selection requires a mux i a[i] a >> a a[0],a[1],a[2],… 0 http://csg.csail.mit.edu/6.S078

  16. Replacing repeated selections by shifts Reg#(Bit#(32)) a <- mkRegU(); Reg#(Bit#(32)) b <- mkRegU(); Reg#(Bit#(32)) prod <-mkRegU();Reg#(Bit#(32)) tp <- mkRegU(); Reg#(Bit#(6)) i <- mkReg(32); rule mulStep if (i < 32);     Bit#(32) m = (a[0]==0)? 0 : b; a <= a >> 1;     Bit#(33) sum = add32(m,tp,0);prod <= {sum[0], (prod >> 1)[30:0]};tp <= sum[32:1]; i <= i+1;endrule http://csg.csail.mit.edu/6.S078

  17. Sequential Multiply bIn aIn s1 b &……………& 0 << 0 s1 +1 << add s1 s1 0 32:1 [30:0] 31 prod a i tp s2 s2 s2 s2 31:0 0 == 32 done result (high) result (low) s1 = start_en s2 = start_en | !done http://csg.csail.mit.edu/6.S078

  18. Int#(32) Int#(32) start en rdy Multiply module Int#(64) rdy result Multiply Module implicit conditions interfaceMultiply; methodAction start (Int#(32) a, Int#(32) b); methodInt#(64) result(); endinterface Many different implementations can provide the same interface: module mkMultiply (Multiply) http://csg.csail.mit.edu/6.S078

  19. Multiply Module module mkMultiply32 (Multiply32); Reg#(Bit#(32)) a <- mkRegU(); Reg#(Bit#(32)) b <- mkRegU(); Reg#(Bit#(32)) prod <-mkRegU();Reg#(Bit#(32)) tp <- mkRegU(); Reg#(Bit#(6)) i <- mkReg(32);rule mulStep if (i < 32); Bit#(32) m = (a[0]==0)? 0 : b;     Bit#(33) sum = add32(m,tp,0);    prod <= {sum[0], (prod >> 1)[30:0]};tp <= sum[32:1]; a <= a >> 1; i <= i+1; endrule method Action start(Bit#(32) aIn, Bit#(32) bIn) if (i == 32); a <= aIn; b <= bIn; i <= 0; tp <= 0; prod <= 0; endmethod method Bit#(64) result() if (i == 32); return {tp,prod}; endmethodendmodule State Internal behavior External interface http://csg.csail.mit.edu/6.S078

  20. Module: Method Interface bIn s1 aIn aIn bIn en rdy b &……………& start 0 s1 << 0 s1 +1 << add s1 s1 0 [30:0] 31 32:1 a i s2 s2 s2 s2 result rdy prod tp 31:0 0 result == 32 result (low) result (high) done s1 = start_en s2 = start_en | !done s1 OR s2 http://csg.csail.mit.edu/6.S078

  21. Tadd(n+n) n n n n TAdd#(n,n) Int#(32) Int#(32) start enab rdy Multiply module Int#(64) rdy #(Numeric type n) result Polymorphic Multiply Module ncould be Int#(32), Int#(13), ... • The module can easily be made polymorphic implicit conditions interfaceMultiply; methodAction start (Int#(32) a, Int#(32) b); methodInt#(64) result(); endinterface http://csg.csail.mit.edu/SNU

  22. Sequential n-bit multiply modulemkMultiplyN (MultiplyN); Reg#(Bit#(n)) a <- mkRegU(); Reg#(Bit#(n)) b <- mkRegU(); Reg#(Bit#(n)) prod <-mkRegU();Reg#(Bit#(n)) tp <- mkRegU(); Reg#(Bit#(Add#(Tlog(n),1)) i <- mkReg(n); nv = valueOf(n);rule mulStep if (i < nv); Bit#(n) m = (a[0]==0)? 0 : b;     Bit#(TAdd#(n,1)) sum = addn(m,tp,0);    prod <= {sum[0], (prod >> 1)[(nv-2):0]};tp <= sum[n:1]; a <= a >> 1; i <= i+1; endrule method Action start(Bit#(n) aIn, Bit#(n) bIn) if (i == nv); a <= aIn; b <= bIn; i <= 0; tp <= 0; prod <= 0; endmethod method Bit#(TAdd#(n,n)) result() if (i == nv); return {tp,prod}; endmethodendmodule http://csg.csail.mit.edu/6.S078

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