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Sequential Circuits

Combinational Circuit. Inputs. Outputs. Memory Elements. Combinational Circuit. Inputs. Outputs. Flip-flops. Clock. Sequential Circuits. Asynchronous Synchronous. Latches. SR Latch. Q = Q 0. 0. 0. 1. 0. Initial Value. Latches. SR Latch. Q = Q 0. Q = Q 0. 0. 1. 0.

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Sequential Circuits

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  1. Combinational Circuit Inputs Outputs MemoryElements Combinational Circuit Inputs Outputs Flip-flops Clock Sequential Circuits • Asynchronous • Synchronous

  2. Latches • SR Latch Q = Q0 0 0 1 0 Initial Value Eastern Mediterranean University

  3. Latches • SR Latch Q = Q0 Q = Q0 0 1 0 0 Eastern Mediterranean University

  4. Latches • SR Latch Q = Q0 Q = 0 1 0 1 0 Eastern Mediterranean University

  5. Latches • SR Latch Q = Q0 Q = 0 1 1 Q = 0 0 0 Eastern Mediterranean University

  6. Latches • SR Latch Q = Q0 0 Q = 0 0 Q = 1 1 1 Eastern Mediterranean University

  7. Latches • SR Latch Q = Q0 0 Q = 0 1 Q = 1 Q = 1 0 1 Eastern Mediterranean University

  8. Latches • SR Latch Q = Q0 1 Q = 0 0 Q = 1 Q = Q’ 1 0 1 Eastern Mediterranean University

  9. Latches • SR Latch Q = Q0 1 Q = 0 1 0 Q = 1 Q = Q’ Q = Q’ 0 1 Eastern Mediterranean University

  10. Latches • SR Latch No change Reset Set Invalid Invalid Set Reset No change Eastern Mediterranean University

  11. Latches • SR Latch No change Reset Set Invalid Invalid Set Reset No change Eastern Mediterranean University

  12. Controlled Latches • SR Latch with Control Input No change No change Reset Set Invalid Eastern Mediterranean University

  13. Controlled Latches • D Latch (D = Data) Timing Diagram C D Q t Output may change No change Reset Set Eastern Mediterranean University

  14. Controlled Latches • D Latch (D = Data) Timing Diagram C D Q Output may change No change Reset Set Eastern Mediterranean University

  15. C CLK Positive Edge CLK Negative Edge Flip-Flops • Controlled latches are level-triggered • Flip-Flops are edge-triggered Eastern Mediterranean University

  16. D Latch (Master) D Latch (Slave) D D C Q D C Q Q CLK Flip-Flops • Master-Slave D Flip-Flop Master Slave CLK D Looks like it is negative edge-triggered QMaster QSlave Eastern Mediterranean University

  17. D Q Q Q D Q Flip-Flops • Edge-Triggered D Flip-Flop Positive Edge Negative Edge Eastern Mediterranean University

  18. Q J Q K Flip-Flops • JK Flip-Flop D=JQ’+K’Q Eastern Mediterranean University

  19. T D Q Q Q Q Q T J Q T K Flip-Flops • T Flip-Flop D=JQ’+K’Q D=TQ’+T’Q=T Q Eastern Mediterranean University

  20. D T Q Q Q Q Q J Q K Flip-Flop Characteristic Tables Reset Set No change Reset Set Toggle No change Toggle Eastern Mediterranean University

  21. D T Q Q Q Q Q J Q K Flip-Flop Characteristic Equations Q(t+1) =D Q(t+1) =JQ’ + K’Q Q(t+1) =TQ Eastern Mediterranean University

  22. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation No change Reset Set Toggle Eastern Mediterranean University

  23. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation No change Reset Set Toggle Eastern Mediterranean University

  24. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation No change Reset Set Toggle Eastern Mediterranean University

  25. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation No change Reset Set Toggle Eastern Mediterranean University

  26. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation Q(t+1) =JQ’ + K’Q Eastern Mediterranean University

  27. Q R D Q Reset Flip-Flops with Direct Inputs • Asynchronous Reset Eastern Mediterranean University

  28. Q R D Q Reset Flip-Flops with Direct Inputs • Asynchronous Reset Eastern Mediterranean University

  29. PR Q D Q Preset Reset CLR Flip-Flops with Direct Inputs • Asynchronous Preset and Clear Eastern Mediterranean University

  30. PR Q D Q Preset Reset CLR Flip-Flops with Direct Inputs • Asynchronous Preset and Clear Eastern Mediterranean University

  31. PR Q D Q Preset Reset CLR Flip-Flops with Direct Inputs • Asynchronous Preset and Clear Eastern Mediterranean University

  32. Analysis of Clocked Sequential Circuits • The State • State = Values of all Flip-Flops Example AB= 0 0 Eastern Mediterranean University

  33. Analysis of Clocked Sequential Circuits • State Equations A(t+1)=DA =A(t) x(t)+B(t) x(t) =Ax + Bx B(t+1)=DB =A’(t) x(t) =A’x y(t)=[A(t)+ B(t)] x’(t) =(A + B) x’ Eastern Mediterranean University

  34. Analysis of Clocked Sequential Circuits • State Table (Transition Table) 0 00 0 10 0 01 1 10 0 01 1 00 0 01 1 00 A(t+1)=Ax + Bx B(t+1)=A’x y(t)=(A + B) x’ t t+1 t Eastern Mediterranean University

  35. Analysis of Clocked Sequential Circuits • State Table (Transition Table) t t+1 t A(t+1)=Ax + Bx B(t+1)=A’x y(t)=(A + B) x’ Eastern Mediterranean University

  36. Analysis of Clocked Sequential Circuits • State Diagram AB input/output 0/0 1/0 0/1 0 0 1 0 0/1 1/0 0/1 1/0 0 1 1 1 1/0 Eastern Mediterranean University

  37. D Q x A Q y CLK Analysis of Clocked Sequential Circuits • D Flip-Flops Example: 0 1 1 0 1 0 0 1 A(t+1)=DA =Ax y 01,10 0 1 00,11 00,11 01,10 Eastern Mediterranean University

  38. Analysis of Clocked Sequential Circuits • JK Flip-Flops Example: 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1 JA = B KA = B x’ JB = x’ KB = A  x A(t+1)=JA Q’A + K’A QA = A’B + AB’ + Ax B(t+1)=JB Q’B + K’B QB = B’x’ + ABx + A’Bx’ Eastern Mediterranean University

  39. Analysis of Clocked Sequential Circuits • JK Flip-Flops Example: 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 0 1 1 Eastern Mediterranean University

  40. Analysis of Clocked Sequential Circuits • T Flip-Flops Example: 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 TA = B x TB = x y = A B A(t+1)=TA Q’A + T’A QA = AB’ + Ax’ + A’Bx B(t+1)=TB Q’B + T’B QB = x  B Eastern Mediterranean University

  41. Analysis of Clocked Sequential Circuits • T Flip-Flops Example: 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0/0 0/0 0 0 0 1 1/0 1/1 1/0 1 1 1 0 0/1 0/0 1/0 Eastern Mediterranean University

  42. Mealy and Moore Models The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15). The outputs may change if the inputs change during the clock pulse period. The outputs may have momentary false values unless the inputs are synchronized with the clocks. The Moore model: the outputs are functions of the present state only (Fig. 5-20). The outputs are synchronous with the clocks. Eastern Mediterranean University

  43. Mealy and Moore Models Fig. 5.21 Block diagram of Mealy and Moore state machine Eastern Mediterranean University

  44. Mealy and Moore Models Mealy Moore For the same state,the output does not change with the input For the same state,the outputchanges with the input Eastern Mediterranean University

  45. Moore State Diagram State /Output 0 0 1 0 0 /0 0 1 / 0 1 1 1 1 / 1 1 0 / 0 1 0 0 Eastern Mediterranean University

  46. State Reduction and Assignment Fig. 5.25 State diagram State ReductionReductions on the number of flip-flops and the number of gates. • A reduction in the number of states may result in a reduction in the number of flip-flops. • An example state diagram showing in Fig. 5.25. Eastern Mediterranean University

  47. State Reduction Fig. 5.25 State diagram • Only the input-output sequences are important. • Two circuits are equivalent • Have identical outputs for all input sequences; • The number of states is not important. Eastern Mediterranean University

  48. Equivalent states • Two states are said to be equivalent • For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state. • One of them can be removed. Eastern Mediterranean University

  49. Reducing the state table • e = g (remove g); • d = f (remove f); Eastern Mediterranean University

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