Design Entry: Schematic Capture and VHDL

Design Entry: Schematic Capture andVHDL ENG2410: Digital Design Week #4

References • Kenneth Sort, “VHDL For Engineers”, Prentice Hall, 2009. • Peter Ashenden, “The designer’s guide to VHDL, 2nd edition”, Morgan Kaufmann publishers, 2002. • Douglas Perry, “VHDL”, 3rd Edition, McGraw Hill. • Sudhakar Yalamanchili, “Introductory VHDL: From Simulation to Synthesis”, Prentice Hall, 2001. • Sudhakar Yalamnachili, “VHDL: A Starter’s Guide”, 2nd Edition, Prentice Hall, 2005.

Design Entry • Schematic capture • What you already did in previous labs. • Hardware Description Language (HDL) • VHDL • Verilog • Electronic System Level (ESL) Higher level possible – C-like and Java-like • ImpulseC, HandelC, Catapult C, Vivado HLS

Schematic Design

What is HDL? Hardware Description Languages (HDLs) are languages used to • document (model), • Communicate design, • simulate, and • synthesize digital circuits and systems.

VHDL: Introduction • VHDL is an acronym for “VHSICHardware Description Language”. • VHSIC is an acronym for “Very High Speed Integrated Circuits” program. It was a US government sponsored program that was responsible for developing a standard HDL. • VHDL supports modeling and simulation of digital systems at various levels of design abstraction.

Internal Functionality External Interface Basic Modeling Concepts circuit A E B Outputs Inputs

Basic Modeling Concepts

Entity name Port name Port Port mode Basic Modeling Concepts External Interface modeled by “entity” VHDL construct. entity ckt1 is port (X,Y,Z : in bit; F : out bit); end entity ckt1; VHDL “port” construct models data input/output.

Entity name Architecture name Basic Modeling Concepts Internal Functionality modeled by “architecture” VHDL construct architecture behav of ckt1 is begin F <= X or (not Y and Z); end architecture behav;

Lexical Elements • Comments: - A comment line in VHDL is represented by two successive dashes “- -”. • A comment extends from “- -” to the end of the line. • Identifiers: • Identifiers are names that can be given by the user. • rules: >> must start with an alphabetic letter. >> can contain alphabetic letters, decimal digits and underline character “_”. >> cannot end with “_”. >> cannot contain successive “_”.

Legal vs. Illegal Identifiers • Valid identifiers • A, X0, counter, Next_Value • Invalid identifiers • last@value  contains illegal character • 5bit_coutner  starts with nonalphabetic • _A0  starts with an underline • A0_  ends with underline • clock__pulses  two successive underlines

Libraries • A library refers to a collection of declarations (type, entity, sub-program) and their implementations (architecture, sub-program body). • The actual specification of a library varies from one simulation package to another. • In VHDL we usually use the IEEE library and have to declare that at the beginning of our VHDL program.

Library: Example • For standard logic (std_logic) the basic package is ieee.std_logic_1164. • This package defines the values and basic logic operators for type std_logic. • The declarations can be made visible in our model file by : library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Library Package

std_logic type Demystified • Signals are used to connect different parts of a design. • They can be thought of as “wires” in conventional sense. • Every signal has a type.

Complete Program -- Library Declaration Library IEEE; Use IEEE.std_logic_1164; -- Entity Declaration Entity ckt1 is Port (X,Y,Z : in std_logic; F : out std_logic); end ckt1; -- Architecture Declaration architecture behav of ckt1 is begin F <= X or not Y and Z; end architecture behav;

dataflow VHDL Design Styles VHDL Design Styles behavioral (algorithmic) structural Components and interconnects Concurrent statements Sequential statements • Registers • State machines • Test benches Subset most suitable for synthesis

Example 2: Signals Internal Signals This circuit could be modelled as following: f <=zorw; z <= xandy; x <= not a; w <=aandb; y <= not b;

Complete Program -- Library Declaration Library IEEE; Use IEEE.std_logic_1164; -- Entity Declaration Entity ckt2 is Port (a, b : in std_logic; F : out std_logic); end ckt2; -- Architecture Declaration architecture dataflow of ckt2 is signal x, y, z, w; begin f<=zorw; z <=xandy; x <=nota; w <=a andb; y <=notb; end architecture dataflow; Internal Signals

Bit type • Bit is also a predefined enumerated type type bit is (‘0’, ‘1’); • Operations • Logical:=, /=, <, >, <=, >= • Boolean:and, or, nand, nor, xor, xnor, not • Shift:sll, srl, sla, sra, rol, ror

Mapping the Design onto Digilent FPGA Board Netlist -- Library Declaration Library IEEE; Use IEEE.std_logic_1164; -- Entity Declaration Entity ckt1 is Port (X,Y,Z : in std_logic; F : out std_logic); end ckt1; -- Architecture Declaration architecture behav of ckt1 is begin F <= X or not Y and Z; end architecture behav; Synthesis Map, Place and Route Generate Bitstream Download 000111010100000000011111001010101010000010100101010101010001100101010110011000

Design Entry: Schematic Capture and VHDL