VHDL

1. VHDL Rabee Shatnawi & Rami Haddad

2. What is this presentation about?! This presentation will introduce the key concepts in VHDL and the important syntax required for most VHDL designs,

3. Why to use VHDL? In most cases, the decision to use VHDL over other languages such as Verilog or SystemC, will have less to do with designer choice, and more to do with software availability and company decisions…. Or the professor's choice ;-)

4. Verilog has come from a ‘bottom-up’ tradition and has been heavily used by the IC industry for cell-based design, • whereas the VHDL language has been developed much more from a ‘topdown’ perspective. Of course, these are generalizations and largely out of date in a modern context

6. Entity: model interface • The entity defines how a design element described in VHDL connects to other VHDL models … • and also defines the name of the model. • It allows the definition of any parameters that are to be passed into the model using hierarchy.

7. Entity definition entity test is …. end entity test; • or: entity test is … end test;

8. Ports • How to connect Entities together? -The method of connecting entities together is using PORTS. • PORTS are defined in the entity using the following method: port ( ...list of port declarations... );

9. The port declaration defines the type of connection and direction where appropriate. port ( in1, in2 : in bit; out1 : out bit );

10. Entity Port Modes • in: • signal values are read-only • out: • signal values are write-only • buffer: • comparable to out • signal values may be read, as well • inout: • bidirectional port

11. Generics If the model has a parameter, then it is defined using generics. generic ( gain : integer := 4; time_delay : time = 10 ns );

12. Constants • It is also possible to include model specific constants in the entity using the standard declaration of constants method constant : rpullup : real := 1000.0;

13. a complete examples, meet our first Entity……. test entity test is port ( in1, in2 : in bit; out1 : out bit ); generic ( gain : integer := 4; time_delay : time := 10 ns ); constant : rpullup : real := 1000.0; end entity test;

14. Architecture: model behavior • Implementation of the design • Always connected with a specific entity • one entity can have several architectures • entity ports are available as signals within the architecture • Contains concurrent statements

15. Basic definition of an architecture • While the entity describes the interface and parameter aspects of the model ………. • the architecture defines the behavior.

16. any local signals or variables can be declared here • There are several types of VHDL architecture and …. • VHDL allows different architectures to be defined for the same entity. architecture behaviour of test is ..architecture declarations begin ...architecture contents end behaviour;

17. Signals • Signals are the primary objects describing the hardware system and are equivalent to “wires”. • They represent communication channels among concurrent statements of system application. • Signals can be declared in: • Package declaration • Architecture • Block: • Subprograms:

18. Hierarchical design • Functions • Packages • Components • Procedures

19. Functions • A simple way of encapsulating behavior in a model that can be reused in multiple architectures. • Can be defined locally to an architecture or more commonly in a package

20. The simple form of a function is to define a header with the input and output variables as shown below: function name (input declarations) return output_type is ... variable declarations begin ... function body end

21. function mult (a,b : integer) return integer is begin return a * b; end;

22. The header: is the place where the types and functions are declared package body: where the declarations themselves take place Package : Function containers package name is ...package header contents end package; package body name is ... package body contents end package body;

23. Component

25. library ieee; use ieee.std_logic_1164.all; -- here is the entity entity halfadd is port (a, b : in std_logic; sum, c : out std_logic); end halfadd; architecture comp of halfadd is begin -- a concurrent statement implementing the and gate c <= a and b; -- a concurrent statement implementing the xor gate sum <= a xor b; end comp;

26. library ieee; use ieee.std_logic_1164.all; entity fulladd is port (ina, inb, inc : in std_logic; sumout, outc : out std_logic); end fulladd; architecture top of fulladd is component halfadd port (a, b : in std_logic; sum, c : out std_logic); end component; signal s1, s2, s3 : std_logic; begin -- a structural instantiation of two half adders h1: halfadd port map( a => ina, b => inb, sum => s1, c => s3); h2: halfadd port map( a => s1, b => inc, sum => sumout, c => s2); outc <= s2 or s3; end top;

27. VHDL • Case insensitive • Comments: '--' until end of line Statements are terminated by ';'(may span multiple lines) • List delimiter: ',' • Signal assignment: '<=‘ • User defined names: • letters, numbers, underscores • start with a letter

28. VHDL …. Identifier mySignal_23      -- normal identifierrdy, RDY, Rdy    -- identical identifiersvector_&_vector  --  X : special characterlast of Zout     --  X : white spacesidle__state      --  X : consecutive underscores24th_signal      --  X : begins with a numeralopen, register   --  X : VHDL keywords (Normal) Identifier Letters, numerals, underscores Case insensitive No two consecutive underscores Must begin with a letter Not a VHDL keyword

29. VHDL Structural Elements Entity : Interface Architecture : Implementation, behavior, function Configuration : Model chaining, structure, hierarchy Process : Concurrency, event controlled Package : Modular design, standard solution, data types, constants Library : Compilation, object code

30. Hierarchical Model Layout VHDL allows for a hierarchical model layout, which means that a module can be assembled out of several submodules. The connections between these submodules are defined within the architecture of a top module. As you can see, a fulladder can be built with the help of two halfadders (module1, module2) and an OR gate (module3).

31. Component :example ENTITY half_adder IS PORT ( A, B : IN STD_LOGIC; sum, carry : OUT STD_LOGIC ); END half_adder; ARCHITECTURE structural OF half_adder IS COMPONENT xor2 PORT ( a, b : IN STD_LOGIC; c : OUT STD_LOGIC ); END COMPONENT; COMPONENT and2 PORT ( a, b : IN STD_LOGIC; c : OUT STD_LOGIC ); END COMPONENT; BEGIN ex1 : xor2 PORT MAP ( a => a, b => b, c => sum ); or1 : and2 PORT MAP ( a => a, b => b, c => carry ); END structural; begin    MODULE1: HALFADDER port map( A, B, W_SUM, W_CARRY1 );    MODULE2: HALFADDER port map ( W_SUM, CARRY_IN,                      SUM, W_CARRY2 );    MODULE3: ORGATE port map ( W_CARRY2, W_CARRY1, CARRY );end STRUCT; entity FULLADDER is   port (A,B, CARRY_IN: in   bit;           SUM, CARRY:     out bit);end FULLADDER;architecture STRUCT of FULLADDER is   signal W_SUM, W_CARRY1, W_CARRY2 : bit; component  HALFADDER      port (A, B :                in   bit;              SUM, CARRY : out bit); end component; component  ORGATE      port (A, B : in   bit;              RES : out bit); end component;begin begin    MODULE1: HALFADDER                     port map (  A           => A,                                     SUM     => W_SUM,                                      B           => B,                                     CARRY => W_CARRY1 );   . . .end STRUCT; ENTITY and2 IS PORT ( a, b : IN STD_LOGIC; output : OUT STD_LOGIC ); END and2; ARCHITECTURE gate OF and2 IS BEGIN output <= ( a AND b ) AFTER 5ns; END gate

32. Process • The process in VHDL is the mechanism by which sequential statements can be executed in the correct sequence, and with more than one process, concurrently. • Contains sequentially executed statements • Exist within an architecture, • only Several processes run concurrently • Execution is controlled either via sensitivity list (contains trigger signals), or wait-statements

33. Process JustToShow: process Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; Some statement 5; end process JustToShow; JustToShow: process Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; wait<condition>; end process JustToShow; • Wait for type expression • Wait until condition • Wait on sensitivity list • Complex wait Wait for 10ns Wait until CLK=‘1’ Wait on Enable Wait unit date after 10ns

34. Process JustToShow: process ( ) Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; end process JustToShow; JustToShow: process Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; wait on end process JustToShow; SomeSig VHDL provides a construct called sensenitivity list of a process The list specified next to the process keyword. The same as wait on sensitivity_list at the end of a process

35. Process Signal2 has changed Signal3 has changed JustToShow: process (signa1,signal2,signal3) Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; Some statement 5; end process JustToShow;

36. Example: Signa1= 0 Signal3=5 6

37. Example: A<=2 A<=D+1 A=1 B=1 C=1 D=1 E=1 3 2 B<=A+C; E<=A*2; 2 process(C,D) begin A<=2; B<=A+C; A<=D+1; E<=A*2; end process;

38. Variables Variables are available within processes Named within process declarations Known only in this process Immediate assignment An assignment to a variable is made with := symbol. The assignment take instance effect and each variable can be assigned new values as many times as needed. A variable declaration look similar to a signal declaration and starts with variable keyword Keep the last value Possible assignments Signal to variable Variable to signal Types have to match

39. Variables vs. Signals Signals In a process, only the last signal assignment is carried out Assigned when the process execution is suspended “<=“ to indicate signal assignment Variables Assigned immediately The last value is kept “:=“ to indicate variable assignment

40. Variables vs. Signals (contd.) A C + X + X B B C C + Y + Y B B

41. Variables process(C,D) Variable Av,Bv,Ev :integer :=0; begin A<=2; Bv<=Av+C; Av<=D+1; Ev <= Av*2; A <=Av; B <=Bv; E <=Ev; end process

42. The world is not sequential Its convention to specify things in a sequential way, this is not the simplest way to describe reality. Processes are concurrent statements Several processes run parallel linked by signals in the sensitivity list sequential execution of statements Link to processes of other entity/architecture pairs via entity interface

43. P2:process(A,C) Begin Somestatment; Somestatment; Somestatment; End process P1; P3:process(B,D) Begin Somestatment; Somestatment; Somestatment; End process P1; end Architecture SomeArch ; Architecture SomeArch of SomeEnt is Begin P1:process(A,B,E) Begin Somestatment; Somestatment; Somestatment; D<=Someexpression;; End process P1;

44. IF Statement:

45. Case statement

46. For loop entity FOR_LOOP is   port (A : in    integer range 0 to 3;           Z  : out bit_vector (3 downto 0)); end FOR_LOOP;architecture EXAMPLE of FOR_LOOP isbegin      process (A)   begin      Z <= "0000"; for  I  in  0 to 3  loop         if (A = I) then            Z(I) <= `1`;         end if; end loop;   end process;end EXAMPLE;

48. Exit & Next • The exit command allows a FOR loop to be exited completely. This can be useful when a condition is reached and the remainder of the loop is no longer required. The syntax for the exit command is shown below: for i in 0 to 7 loop if ( i = 4 ) then exit; endif; endloop; • The next command allows a FOR loop iteration to be exited, this is slightly different to the exit command in that the current iteration is exited, but the overall loop continues onto the next iteration. This can be useful when a condition is reached and the remainder of the iteration is no longer required. An example for the next command is shown below: for i in 0 to 7 loop if ( i = 4 ) then next; endif; endloop;

49. Conditional Signal Assignment • TARGET <= VALUE;TARGET <= VALUE_1 when CONDITION_1 else                    VALUE_2 when CONDITION_2 else                    . . .                    VALUE_n; entity CONDITIONAL_ASSIGNMENT is   port (A, B, C, X : in   bit_vector (3 downto 0);            Z_CONC : out bit_vector (3 downto 0);            Z_SEQ    : out bit_vector (3 downto 0));end CONDITIONAL_ASSIGNMENT;architecture EXAMPLE of CONDITIONAL_ASSIGNMENT isbegin   -- Concurrent version of conditional signal assignment Z_CONC <= B when X = "1111" else                        C when X > "1000" else                        A;   -- Equivalent sequential statements  process (A, B, C, X)   begin if  (X = "1111")  then         Z_SEQ <= B; elsif  (X > "1000")  then         Z_SEQ <= C;      else         Z_SEQ <= A; end if;   end process;end EXAMPLE;

50. Selected Signal Assignment with EXPRESSION select  TARGET <= VALUE_1 when CHOICE_1,                       VALUE_2 when CHOICE_2 | CHOICE_3,                       VALUE_3 when CHOICE_4 to CHOICE_5,                       · · ·                       VALUE_n when others; • entity SELECTED_ASSIGNMENT is   port (A, B, C, X : in   integer range 0 to 15;            Z_CONC : out integer range 0 to 15;            Z_SEQ    : out integer range 0 to 15);end SELECTED_ASSIGNMENT; architecture EXAMPLE of SELECTED_ASSIGNMENT isbegin    -- Concurrent version of selected signal assignment with X select      Z_CONC <= A when 0,                           B when 7 | 9,                           C when 1 to 5,                           0 when others;   -- Equivalent sequential statementsprocess (A, B, C, X)   begin      case X is         when 0         => Z_SEQ <= A;         when 7 | 9    => Z_SEQ <= B;         when 1 to 5  => Z_SEQ <= C;         when others => Z_SEQ <= 0;   end process;end EXAMPLE;