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Error Correction and Partial Information Rewriting for Flash Memories

Error Correction and Partial Information Rewriting for Flash Memories. Yue Li joint work with Anxiao (Andrew) Jiang and Jehoshua Bruck. Block Erasure is Harmful. Decreasing cell level triggers block erasure E rasure degrades cell quality.

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Error Correction and Partial Information Rewriting for Flash Memories

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  1. Error Correction and Partial Information Rewriting for Flash Memories Yue Li joint work with Anxiao (Andrew) Jiang and JehoshuaBruck

  2. Block Erasure is Harmful • Decreasing cell level triggers block erasure • Erasure degrades cell quality E. Cohen, “The Nibbles and Bits of SSD Data Integrity”, Flash Memory Summit, 2013.

  3. Solutions based on Coding • Codes for Rewriting • Floating Codes [2] • Buffer Codes [3] • Rank Modulation [4] • WOM [5, 6, 7] Error Correcting Codes [2] A. Jiang, V. Bohossian, and J. Bruck, "Floating Codes for Joint Information Storage in Write Asymmetric Memories,” ISIT, 2007. [3] V. Bohossian, A. Jiang, and J. Bruck, "Buffer Coding for Asymmetric Multi-Level Memory,” ISIT 2007. [4] A. Jiang, R. Mateescu, M. Schwartz, and J. Bruck, "Rank Modulation for Flash Memories,” IEEE Transactions on Information Theory , 2009. [5] R. L. Rivest and A. Shamir, “How to reuse a ‘Write-Once’ memory,” Information and Control, vol. 55, pp. 1–19, 1982. [6] E. Yaakobi, S. Kayser, P. H. Siegel, A. Vardy, J. K. Wolf, "Codes for Write-Once Memories,” IEEE Transactions on Information Theory, 2012. [7] D. Burshtein, and A. Strugatski, "Polar Write Once Memory Codes,” IEEE Transactions on Information Theory, 2012. Trajectory Codes[8] [8] A. Jiang, M. Langberg, M. Schwartz, and J. Bruck, "Trajectory Codes for Flash Memory,” IEEE Transactions onInformation Theory, vol. 59, no. 7, pp. 4530-4541, July 2013.

  4. Write-Once Memory Codes R. L. Rivest and A. Shamir, “How to reuse a ‘Write-Once’ memory,” Information and Control, vol. 55, pp. 1–19, 1982. Write 2 bits twice using 3 cells Example: store 10 then 01 000 010 110

  5. General Rewriting Graph Directed, Strongly Connected Graph G(V, E) 0 Allowed Transition 1 7 2 6 Data State 5 3 4

  6. Performance Measure A message M0 is updated K-1 times following (M1, M2, …, MK-1) Total number of message bits Sum Rate = K log2|V| / N (bits/cell) Total number of cells Example: for R-S WOM code, K = 2, |V| = 4, N = 3. Sum Rate = 4 / 3 = 1.33 bits / cell > 1 bit/cell

  7. Partial General Rewriting Graph Directed, Strongly Connected Graph G(V, E) 0 Allowed Transition 1 7 2 6 Data State 5 3 Maximum outdegree<< |V| 4

  8. Motivation of Partial Rewriting Remote File Synchronization Server Dropbox or Mobile App Server Synchronization Synchronization Update A C B

  9. ? for Noisy Cells Trajectory Codes a 5 a 1 b 0 2 … Register A register is a group of cells Store 0 BSC(p) BSC(p) BSC(p) BSC(p) BSC(p) BSC(p) Update to 1 Update to 2 log2|V| bits log2|D| < log2|V| !! Update to 5 A register goes through a BSC(p) between two updates. [1] A. Jiang, M. Langberg, M. Schwartz, and J. Bruck, "Trajectory Codes for Flash Memory,” IEEE Transactions onInformation Theory, vol. 59, no. 7, pp. 4530-4541, July 2013.

  10. Construction 1 (Example: C = 3, t = 2, K = 6) a 5 a 1 b 0 2 … Corrects BSC(p*3) Corrects BSC(p*2) Corrects BSC(p) Update to Update to Update to Write 1 2 5 0 BSC(p) BSC(p) BSC(p) BSC(p) BSC(p) BSC(p)

  11. Bounds on Achievable Code Rates Sum Rate = K log2|V| / N (bits/cell) N = N0 + N1 + … + Nc-2 + Nc-1 Instant rate of the j-th write of the i-th ECC-WOM code N0= log2 |V| / minjR0,j Ni = log2 D / minjRi,j if i > 0 Upperbounds and lowerbounds of R0,j and R0,j can be derived with Polar ECC-WOM [2] [2] A. Jiang, Y. Li, E. En Gad, M. Langberg, and J. Bruck, “Joint Rewriting and Error Correction for Write-Once Memories,” ISIT, 2013.

  12. Performance of Construction 1 • Compare the bounds of three cases • Max degree: D is larger 21024 • D is smaller 213 • Basic ECC-WOM using only 1 register • Parameters • Message length: log2|V| = 1KByte (213 bits) • Number of registers: C = 8 • Channel error rate p = 10-3

  13. Performance of Construction 1

  14. Construction 2 (Example: C = 3, t = 2, K = 6) a 5 a 1 b 0 2 … Recover S2by decoding S’2 = S2 + BSC(p) Recover S0by decoding (S’’0 + (S0 + S’0)) = S0 + BSC(p) Recover S1by decoding S’1 = S1+ BSC(p) Recover S1by decoding (S’’1 + (S1 + S’1))= S1+ BSC(p) Recover S0by decoding S’0 = S0 + BSC(p) Recover S0by decoding (S’’’0 + (S0 + S’0) +(S’0 + S’’0))= S0 + BSC(p) Corrects BSC(p) Corrects BSC(p) Corrects BSC(p) Write 0 BSC(p) BSC(p) BSC(p) BSC(p) BSC(p) BSC(p) S0 1 S’0 S1 2 S2 S’1 S’’0 Read 2 S’2 S’’’0 S’’1

  15. Performance of Construction 2

  16. Generalizations • When t = 1and M0 = M1 = …= MK-1 • Erasure-free memory scrubbing [3] • Error correction pointer [4] Error Logging Area Information Storage Area [3] Y. Li, A. Jiang, and J. Bruck, ”Multiphase Scrubbing for Phase-Change Memories,” Technical Report, 2013. [4] S. Schechter, G. Loh, K. Straus, and D. Burger, “Use ECP, not ECC, for hard failures in resistive memories.” In Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10), 2010.

  17. Generalizations (2) • Error correction support for all kinds of rewriting codes! Buffer Codes [3] WOM [5,6,7] Floating Codes [2]

  18. Summary • Error correction trajectory codes are • Efficient • when D << |V| • General • Existing practical memory scrubbing/ECP schemes • Error correction for various rewriting codes • Extensible • q-ary? • Asymmetric noise channel ? • Capacity ? Thank You

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