Particles and Fields Package (PFP) PFDPU Peer Review DCB

1. Particles and Fields Package (PFP) PFDPU Peer Review DCB

2. Peer Review Agenda DCB Introduction Changes since PDR Implementation Status Test Environment

3. DCB – a redundant PFDPU Component

4. Data Controller Board Changed with MDM Harness Modification – now directly forwarded to inboard instrument subsystems LPW “Highspeed” clock sent via coax

5. DCB Basic Subsystems (1) • C&DH Interface • Commands arrive via UART (57.6Kbaud) • Telemetry transmitted via UART (57.6Kbaud) • Discrete Commands arrive via Optocouplers • S/C RESET, SC CLK1HZ, SIDESELECT • CPU (as an FPGA subcomponent) • COLDFIRE V1 core • Memory • Boot ROM, EEPROM, CPU SRAM and Instrument SRAM • FLASH – 8Gbytes in two separately powered 4Gbyte modules • Instrument Interface - Mode Setup and Data Ingest • Instrument initialization parameters as outlined in ICDs

6. DCB Basic Subsystems (2) • Basic subsystems (continued) • Timekeeping • SCLK = 16.78 MHz • Provides instrument timebase (Sample Time) • Logic timestamps S/C CLK1Hz with respect to Sample Time • Generates CPU Interrupts and Watchdog Timer Reset • Provides Instrument DMA Buffer Swap “ticks” • Housekeeping • REG forwards analog signal to DCB based ADC (1604) • FSW controls address and enables to REG based analog multiplexors • FSW samples data at regular intervals

7. DCB Evolution since PDR • Processor/Memory • Detailed design defined as FPGA design progressed • Command Buffers change to bytewide • PROM copied to RAM by FPGA prior to deassertion of CPU-RESET • Occurs following any of the three types of resets • One wait state required for CPU Memory • Necessary to meet FPGA FLIGHT PART timing • Performance estimate: at least 5x RBSP DCB Processor (z80 running at the same clock speed) • Processor bus is loaded further when DMA is active (Instrument Data In, FLASH Xfers and S/C Data Out)

8. Worstcase DMA Loading on MBUS • Maximum data rate at the hardware level is tolerated; performance degradation is gradual • Memory arbiter always allows the CPU accesses between adjacent DMA cycles • Buffers are capped by software control => if an instrument is programmed incorrectly, memory is protected. Buffer overflow freezes the DMA controller at the maximum address (a corresponding error status flag set by the hardware) • Operational Instrument Data rate is much lower than the maximums shown. The actual Instrument DMA bus loading (even with instrument diagnostic messages enabled) is approximately 2%. • FLASH DMA impact on processor is much less than maximum (archive data in and S/C Telemetry out) => FLASH DMA duty cycle is less than 10%. Peak rate can be adjusted via throttle option.

9. Miscellaneous changes since PDR(all of minor impact) • EUV door status routed to DCB • Diode protected, pulled up on DCB, door position connect these signals to ground • FPGA provides these signals (EUVDOOROPEN and EUVDOORWIN) to the CPU via a status register • Adjustments to Actuator Subsystem • Pulse durations and guardbands (customized for the various actuator types) • S/C Side Select modified in accordance with S/C ICD Update • Interface change (polarity and behavior – sampled only during power-on)

10. Board Status • Two DCB ETU units fully functional • Plan is to load DCB ETU #3 using the candidate Flight Board Manufacturing subcontractor (Aeroflex Microelectronic Solutions) • In the “request for quotation” phase • FLASH FPGA Daughter board fully functional • also used by the STATIC Digital board • FLIGHT FPGA Daughter board currently in routing phase • Plan is to build the an initial FLIGHT FPGA Daughter board (CGA624) with a “dummy” package in order to verify our subcontractor and manufacturing process (again with Aeroflex Microelectronic Solutions)

11. DCB – Boards and Assembly

12. ETU Power Measurements • 1.5V supply estimate is based on the FLIGHT FPGA Prediction • Latest Flight estimate is 200mA nominal, 450 mA worst case • Worstcase predict based on 17MHz, 75 C • 5VD is only powering the ADC output buffer supply and a buffer/translater • Has been changed to a linear supply • 3.3 V current may be slightly less than we originally predicted

13. FPGA Status (1) • Functional design fully implemented in the FLASH FPGA • Minor changes expected before the final port to the FLIGHT part • Actuator timeout adjustments • Addition of ECC protection to the FPGA based memory subsystems (Command In SRAM and Instrument Command Out FIFO) • Initial port to the target flight FPGA: Flight Part Timing Characterization Flight Part Power Estimate Design MDCBFPGA Family Axcelerator Die RTAX2000S Package 624 CCGA/LGA Radiation Exposure 20 Temperature -55 25 75 Voltage MIL Speed Grade -1 Design State Post-Layout Data source Silicon verified Analysis Min Case BEST Analysis Max Case WORST Scenario for Timing Analysis Primary MAX FREQ SCLK - 18.65MHZ MAX CLK to Q - 30ns Power Summary - TYPICAL (25C) Total Power | 300mW Power Summary - WORSTCASE (75C) Total Power | 700mW

14. FPGA Status (2) Flight Part Utilization Report SEQUENTIAL (R-cells) Used: 6377 Total: 10752 (59.31%) COMB (C-cells) Used: 13837 Total: 21504 (64.35%) LOGIC (R+C cells) Used: 20214 Total: 32256 (62.67%) RAM/FIFO Used: 6 Total: 64 IO w/Clocks Used: 211 Total: 418 CLOCK (Routed) Used: 4 Total: 4 HCLOCK (Hardwired) Used: 1 Total: 4 PLL Used: 0 Total: 0 Input I/O Register : 0 Output I/O Register : 0 DDR Register : 0 Comb-Comb (CC) : 0 Carry Chain : 68 I/O Information: Input Pads : 44 Output Pads : 119 Bidirectional Pads : 48 Differential Input Pairs : 0 Differential Output Pairs : 0

15. Test/Verification • Coldfire Processor • Three alternate means to “run” the processor • Freescale “Codewarrior” simulation • Used for generic software development/verification • Modelsim simulation • Used for FPGA verification (boots from the same “ROM” as the actual DCB) • Can also be used to run the flight software for debug or high-fidelity modeling/characterization • Much slower than the other Coldfire environments, but provides a wealth of information • Stimulus can be carefully controlled (S/C Commands, Instrument Data, etc.) • Actual Board • Debug facility on the DCB facilitates tracing the processor with a logic analyzer (we also have LEDs!) • We have been using the processor realtime for approximately eight months

16. S/C Simulator &MISG Instrument Simulator) • S/C Simulator allows for connection of DCB to GSEOS • 56Kbaud UART, Time and Side Select implemented in hardware • S/C Interface emulated by the GSEOS software • MISG emulates all 8 telemetry interfaces • Plays a unique pattern for each instrument at a programmable repeat period • Controlled by GSEOS

18. DCB Subsystem Diagnostics • DCBMON ported to Coldfire processor • Operates using the S/C simulator UART I/F • Allows for peeking/poking registers and memory • Diagnostic programs added to the ROMMON environment • FLASH Subsystems tests ported from RBSP • Bad block log archived both ETU DCBs • Further tests will be added in parallel to the DCB Test Procedure development

20. Next steps • Refine diagnostic test suite • Instrument DMA (using MISG) • Memory in-system tests • Simultaneous DMA stress test • Optimize components; verify signal integrity • Housekeeping mux filter • Series termination resistors • DCB #3 (high-fidelity PFDPU simulator) • Transition to flight layouts (DCB and Flight FPGA daughter board) • Incorporate MDM37 and Coax for LPW HSCLOCK • Generate DCB Test Procedure • Complete retarget to Flight FPGA • Review for MDCB-FPGA to be held prior to retarget completion

21. Documentation – Design and Analysis • If time permits, walk through: • Schematics (DCB, FPGA Daughter Boards) • PCB Layouts (DCB, FPGA Daughter Boards) • Stress Analysis • MAVEN Particles and Fields Instrument Package PFDPU Data Controller Board Specification

22. Issues/Concerns • CGA624 manufacturing (we are using this package for the first time) • Flight FPGA daughter board routing is process • As a pathfinder, a dummy CGA624 will be populated and the board verified