1 / 21

OUTPUT Pad and Driver

OUTPUT Pad and Driver. CLOCK DRIVER. Buffering. S = scaling or tapering factor CL = S N+1 Cg ……………… All inverters have identical delay of t o = delay of the first stage (load =Cd+Cg). 5. S. 4. 3. 0 1 2 3. Cd/Cg. Buffering.

silver
Download Presentation

OUTPUT Pad and Driver

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. OUTPUT Pad and Driver

  2. CLOCK DRIVER

  3. Buffering S = scaling or tapering factor CL = SN+1 Cg ……………… All inverters have identical delay of to = delay of the first stage (load =Cd+Cg)

  4. 5 S 4 3 0 1 2 3 Cd/Cg Buffering If the diffusion capacitance Cd is neglected, S = e = 2.7

  5. Layout of Large Device

  6. Large Transistor Layout

  7. Output Drivers Standard CMOS Driver Open Drain/Source Driver: Single Transistors Tri-state Driver Bi-directional Circuit

  8. Tri-state Driver V DD En Out In En • Tri-state or High impedance • Used to drive internal or external busses • Two inputs: • Data In and Enable • Various signal assertions • Two types: • C2MOS • CMOS with Control Logic C2MOS

  9. Tri-state Driver V Control logic could be modified to obtain Inversion/non-inversion Active low/high Enable For large load, pre-drivers are required DD En PAD Out En In

  10. Latch-up: Trigger • Factors which trigger latch-up • transmission line reflections or ringing • voltage drop on the VDD bus • “hot plug in” of unpowered circuit board • electrostatic discharge • sudden transient on power and ground busses • leakage current across the junction • radiation: x-ray, cosmic

  11. Input PAD

  12. Protection Circuitry Principles Avalanche Punch Through

  13. Protection Circuitry

  14. Protection Circuitry

  15. Input protection • Electrostatic discharge can take place through transfer of charges from the human body to the device. • Human body can carry up to 8000V. • Discharge can happen within hundreds of nanoseconds. • Critical field for SiO2 is about 7X106 V/cm. • For 0.5u CMOS process the gate oxide can withstand around 8V • Some protection technique is required with minimum impact on performance 1.5K 1M Vesd DUT 100pF Human Body model

  16. ESD Structures Basic technique is to include series resistance and two clamping diodes. The resistance R is to limit the current and to slow down the high voltage transitions. R could be polysilicon or diffusion resistance Diffusion resistance could be part of the diode structure Typical values of R: 500 to 1k VDD R PAD

  17. Layout of ESD Structure PAD n+ p+ Guard Ring Guard Ring p+ p+ n+ n+ This structure uses transistors as clamping diodes

  18. Layout of ESD Structure VDD PAD n+ p+ Guard Ring Guard Ring p+ p+ n+ n+ GND

  19. Another ESD Structure VDD R1 R2 PAD Thick FOX MOS Transistor

  20. Bi-direct PAD V DD Pre-drivers IN ESD Protection Input Buffer PAD Control Logic EN

  21. Thank you !

More Related