Reliability of Antifuse-Based field Programmable Gate Arrays for Military and Aerospace Applications

1. Reliability of Antifuse-Based field Programmable Gate Arrays for Military and Aerospace Applications John McCollum, Roy Lambertson, Jeewicka Ranweera, Jennifer Moriarta, Jih-Jong Wang, Frank Hawley, and Arun Kundu Actel Corporation Figure1

2. The Design Engineer (user) and his CAE tools is partially responsible for the content of an FPGA • Reliability of an FPGA design is therefore a mix of the manufacturer and the user Figure2

3. Manufacturer Responsibility • Antifuses are an addition to the base CMOS process • Reliability of the ONO antifuse • There are two states that must be reliable • Open • Short Figure3

4. N+ Polysilicon Oxide Nitride Oxide N+ Diffusion ONO Antifuse Figure4

5. ONO Antifuse Photomicrograph Figure5

6. Figure6

7. Programmed State of ONO Figure7

8. Note: No Switch off Heating of Filament Programmed at 5mA Figure8

9. ONO Antifuse Switch off Test Figure9

10. Photomicrograph showing Poly Contact failed not the Antifuse Figure10

11. SEDR Curve 90A Thickness Typical is 96A Figure11

12. Amorphous-Silicon Antifuse allow higher density(Sea of Modules) • Higher performance - Lower Capacitance • Reliability analysis for opens and shorts Figure12

13. Unprogrammed Antifuse Via to Metal 4 Antifuse Metal 3 Figure13

14. Life of the Universe Data indicates that this line actually turns up Figure14

15. Programmed Antifuse Figure15

16. Data showing that switch off the metal Antifuse is over designed by at least a factor of 2 Figure16

17. SEDR of the Metal to Metal Antifuse No failure SXS shows one fail at 2.85V max spec is 2.75V Figure17

18. Since BVG (Break Down Voltage) of ONO was lower than gate oxide no antifuses are connected to pins • ESD thus achieved Class 2 >2000 Volts • Actel however discovered PID (Process Induced Damage) in Fabs • Implanters and Plasma Etchers could produce 20 volts on the wafer and destroy the ONO • Actel worked with the Fabs and solved this problem • Additionally Actel voltage stresses each part at Wafer Sort and Final Test to eliminate all antifuse defects Figure18

19. Nominal BVG PID tale Figure19

20. Most MOS reliability defects are traditionally Gate oxide Failures • By virtue of the high voltage stresses applied to Actel circuits for programming (even low voltage transistors) there have been very few oxide failures Figure20

21. Apparent turn up is due to less time to collect long term data Figure21

22. With ten years of production of Multi-Layer Aluminum the process is very mature even though it has been scaled Early defects related to via failures Figure22

23. Due to the high level of integration modern ICs are have progressed dramatically Note: no failures Figure23

24. Testing ASIC s with test vectors of less than 100% can lead to unacceptable failure rates • FPGAs are however 100% tested • All tracks • All modules • All clocks • All programming circuits • All I/Os • All isolation transistors • The charge pump • All antifuses in the open state • All antifuses are stressed • A column of circuits is programmed (binning circuit) to verify programming Figure24

25. Fault Coverage Figure25

26. During programming a small fraction of antifuses will fail to program • Once the programmer passes a part it is guaranteed to be 100% functional • Tests are performed to verify the correct antifuse is programmed and is the correct impedance • Additional tests are done to verify that no other antifuse was erroneously programmed or any circuit damage was done Figure26

27. CAE tools are reliable in translating RTL code to a logic design, but may pitfalls await the designer • Behavior level code would be less prone to bugs, but it will not be very efficient in silicon use or very fast - hence not much demand • Remember with FPGAs YOU are an IC designer • Following are few examples of pitfalls Figure27

28. Without “Preserve” VHDL will delete this buffer Q D Q D >CLK >CLK High Skew Clock A lot of emphasis needs to be placed of timing analysis!! Figure28

29. The designer must know his target FPGA and understand the proper coding style to achieve his design goals • Improper coding will produce a logically correct circuit, but might use combinatorial logic to clock a register rather than merely enabling the register and using the clock Figure29

30. For example, the following Verilog code will synthesize to a two-input AND gate the output of which will clock the register. module gatedFF(Q, Data, Clock, Enable); input Clock, Data, Enable; output Q; reg Q; wire GC; assign = (Clock && Enable); always @(posedge GC) begin Q = Data; end endmodule Figure30

31. Once you rewrite the Verilog in the following way, the tools are able to infer the Enable-FF. module enableFF(Q, Data, Clock, Enable); input Clock, Data, Enable; output Q; reg Q; always @(posedge Clock) begin if (Enable) Q = Data; end endmodule Figure31

32. In space based applications Register Duplication is to be avoided as SEU can easily create illegal states • VHDL requires you to instantiate the special CLKINT or CLKBUF • Synplify has an option to turn register duplication off Figure32

33. If SEU is a concern the use of CC Module or TMR techniques are required. Actel tools fully support these techniques in synthesis • The RTSXS family has self refreshing TMR built into every register. It has proven nearly ion proof, such that SEU upsets do not have to be considered in design Figure33

34. RTSXS have new features to make it power-up friendly while the charge pump is turning on • Outputs are tristated • Logic Modules are in standby • Outputs can be programmed to source or sink 50 a • Once Charge pump has reached operating voltage the modules are activated and the outputs become valid with no glitches Figure34

35. Every FPGA manufacturer will tell their customers “use fully synchronous design” • Yet many designers don’t or manage to avoid fully synchronous design points at critical interfaces • The successful designer will learn his CAE tools and the target FPGA and follow good design practice Figure35

36. User Testing • FLIP FLOPs can remember their last state up to 24 hours • Set flip flops to the opposite state of the desired power-up state for one hour before power-down followed by the power-up sequence • Power-on reset signals should not be applied until the power supplies have reached spec. Figure36

37. Summary • Devices and CAE tools have improved tremendously in 30 years. • Very high levels of integration have made systems more reliable • ICs and CAE tools benefit from multiple users to scrub defects from the circuits • FPGAs have made the system designer an IC designer - ultimately the system reliability rests with him Figure37