1 / 37

Thermal Imaging Test Chip

Thermal Imaging Test Chip. Justin I. Quesnel 08/18/05. Outline. Objective Previous Work Chip Design Chip Test and Results Photos Q & A. Project Objective.

skah
Download Presentation

Thermal Imaging Test Chip

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Thermal Imaging Test Chip Justin I. Quesnel 08/18/05

  2. Outline • Objective • Previous Work • Chip Design • Chip Test and Results • Photos • Q & A

  3. Project Objective • To develop an ideal test structure to prove the theoretical limits of subsurface thermal imaging resolution with a Numerical Aperture Increasing Lens (NAIL).

  4. 100X objective Conventional State-of-the-art 10X w/NAIL Boston Univ. Numerical Aperture Increasing Lens (NAIL) background • Plano-convex lens of the same material • Silicon, n = 3.5 • Without a NAIL, 2.5um • With a NAIL, .73um • Lateral Resolution increase by a factor of n = 3.5

  5. Previous Work • First experiment with NAIL enhancement • Lateral Resolution of 1.4 um • Limitations • Feature size not fine enough • Electromigration • Unknown maximum current density • Environment not easily controlled/measured

  6. New Chip Requirements • Test structures • Different materials/emissivities • Crossing and vertical lines • Varying widths • Internally controlled excitation • Frequency and Pulse-width • Temperature Control

  7. Fabrication Sites • Tradeoffs • Cost vs. Feature Length • Proprietary Information • Submission Dates • Final Decision • AustriaMicrosystems • .35 um feature length • 4 metal layers, 2 poly

  8. Software • Cadence • Design and Electrical Simulation • Femlab • Thermal simulations

  9. Chip Overview • Chip Sections • Samples • Pulse Generator • Thermal Network • Passives • Specifications • 3.3mm x 3.3mm • ~37,000 transistors • 80 pins

  10. Sample Overview • Template • Test structures • M1-M4, P1,P2, Diffusion • Crossing, Vertical

  11. Sample – Test Structures • Test Structures • Varying Widths • Heating resistors • Thermal sensor

  12. Sample - Control • Transmission Gates • Digital Control Logic • Driving Transistors • Max Current Density • Operating Modes

  13. Pulse Generator • Frequency control • Pulse Width Modulation • Test/Bypass points

  14. Thermal Network • Temperature Sensing • Voltage and temperature are linear with a constant current • Biasing and sensing • Current Mirrors • Large mux for toggling between thermal sensors

  15. Advantage of Temperature Control • Voltage Controlled • Heating Resistors in parallel • Ambient temperature • Larger Blackbody Radiation

  16. Advantage of Pulsed Excitation • DC vs Pulsed • Varying Pulsewidth

  17. Fault Tolerance • Backup structures • Completely isolated • Test and Bypass points placed around chip

  18. Passive Structures • Microscope Calibration • All layers

  19. Pad Ring Design • Flip chip bonding • Special Constraints • Limited # of pins • Two Concentric Circles • Accessibility • Pad Design and Protection

  20. Chip Testing • Packaging • Dual Inline Packaged • Electrical Testing • Wirewrapped • Digital toggle switches • Sample<0:3> • First_res<0:3>, Second_res<0:3> • Mode_bits<0:1> • Enable and control bits • Analog

  21. Results • Sample - Test • Passive Resistor Testing • Toggling through samples and resistors • Active Resistor Testing • Exciting internally, viewing externally • Varying pulses • Exciting externally

  22. Results • Function Generator - Test • Ring Oscillator and Counter • Pulse-Width Modulator • Bypassed using external ICs • Test and Bypass Points

  23. Results • Temperature Network - Test • Individual diode • Varying voltage • ~5 Celsius delta • Diode network • Gradient detected • Susceptibility to neighbors • Heat sinks (~2C delta)

  24. Chip Testing Conclusion • All units functioning • Pulse width modulator is malfunctioning • Easily Bypassed with external IC • Ready for next phase • Flip-chip bonding on a PCB

  25. Near Infrared Images • Indium Gallium Arsenide Camera • 1200 nm LED array source

  26. Near Infrared Images • Metal 4 Sample View • Top Side • Obstructed view • Flipped

  27. Near Infrared Images • Top View of Metal 4 lines

  28. Near Infrared Images • Subsurface view of Calibrating Lines

  29. Future Work on Chip • Preparation for thermal imaging • Die polishing • Flip-Chip bonding • Thermal image data acquisition

  30. Limitations • Potential enhancements • Larger die = more IO Pins • More elaborate temperature network • Dedicated voltage control pins • Wider voltage control nets

  31. Summary • Thermal Test Chip • Consists of ~150 different resistive structures • Digitally Controlled • Controllable frequency/pulsewidth • Several Modes of operation • Temperature control • Testing and Results • Fully operational • Ready for thermal imaging

  32. Questions

  33. Near Infrared Images • Sub surface Analog Section • Current Mirrors and Opamp

  34. Near Infrared Images • Top Level Polysilicon Layer 1 Sample

  35. Near Infrared Images • Subsurface view - Digital Control • ~2500 transistors

  36. Near Infrared Images • Subsurface view Driving PMOS transistors

  37. Near Infrared Images • Subsurface view Frequency Control Unit

More Related