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CPE/EE 422/522 Advanced Logic Design L04

This course covers topics such as analysis, synthesis, simplification, hazards, building blocks, PALs, PLAs, ROMs, Mealy and Moore designs, setup and hold times, maximum clock frequency, and state table reduction.

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CPE/EE 422/522 Advanced Logic Design L04

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  1. CPE/EE 422/522Advanced Logic DesignL04 Electrical and Computer EngineeringUniversity of Alabama in Huntsville

  2. Outline • What we know • Combinational Networks • Analysis, Synthesis, Simplification,Hazards, Building Blocks, PALs, PLAs, ROMs • Sequential Networks: Basic Building Blocks • Design: Mealy • Setup and hold times, Max clock frequency • What we do not know • Design: Moore • Equivalent States • State Table Reduction • Intro to VHDL UAH-CPE/EE 422/522 AM

  3. Review: Mealy Sequential Networks General model of Mealy Sequential Network (1) X inputs are changed to a new value • After a delay, the Z outputs and next state appear at the output of CM (3) The next state is clocked into the state register and the state changes UAH-CPE/EE 422/522 AM

  4. x z Q Review: 8421 BCD to Excess3 BCD Code Converter UAH-CPE/EE 422/522 AM

  5. Sequential Network Timing (cont’d) Timing diagram assuming a propagation delay of 10 ns for each flip-flop and gate (State has been replaced with the state of three flip-flops) UAH-CPE/EE 422/522 AM

  6. Setup and Hold Times • For a real D-FF • D input must be stable for a certain amount of time before the active edge of clock cycle => Setup time • D input must be stable for a certain amount of timeafter the active edge of the clock => Hold time • Propagation time: from the time the clock changes to the time the output changes Manufacturers provide minimum tsu, th, and maximum tplh, tphl UAH-CPE/EE 422/522 AM

  7. Maximum Clock Frequency - Max propagation delay through the combinational network - Max propagation delay from the time the clock changes to the flip-flop output changes { = max(tplh, tphl)} - Clock period Example: UAH-CPE/EE 422/522 AM

  8. Hold Time Violation • Occur if the change in Q fed back through the combinational network and cause D to change too soon after the clock edge Hold time is satisfied if: What about X? Make sure that input changes propagate to the flip-flops inputs such that setup time is satisfied. Make sure that X does not change too soon after the clock. If X changes at time ty after the active edge, hold time is satisfied if UAH-CPE/EE 422/522 AM

  9. Moore Sequential Networks Outputs depend only on present state! X = x1 x2... xn Q = Q1 Q2... Qk Z = z1 z2... zm x1 z1 x2 z2 Q xn zm UAH-CPE/EE 422/522 AM

  10. General Model of Moore Sequential Machine Outputs depend only on present state! Combinational Network Outputs(Z) Next State Inputs(X) State(Q) State Register Combinational Network Clock X = x1 x2... xn Q = Q1 Q2... Qk Z = z1 z2... zm UAH-CPE/EE 422/522 AM

  11. S10 S9 S0 S6 S1 S2 S7 S3 S8 S5 S4 1 0 1 1 1 0 0 0 0 0 1 Code Converter: Moore Machine Start 1 0 NC C 1 0 0 1 NC C C 0 1 0 0 1 1 NC NC C 1 0 0 1 0 0 1 NC 1 NC 0 UAH-CPE/EE 422/522 AM

  12. Start S8 S2 S5 S10 S9 S3 S6 S1 S0 S7 S4 1 0 1 1 0 0 0 1 0 1 1 0 0 NC C 1 0 0 1 NC C C 0 1 0 0 1 1 NC NC C 1 0 0 1 0 0 1 NC 1 NC 0 Code Converter: Moore Machine Do we need state S0? How many states does Moore machine have?How many states does Mealy machine have? UAH-CPE/EE 422/522 AM

  13. Start S8 S2 S5 S10 S9 S3 S6 S1 S0 S7 S4 1 0 1 1 0 0 0 1 0 1 1 0 0 NC C 1 0 0 1 NC C C 0 1 0 0 1 1 NC NC C 1 0 0 1 0 0 1 NC 1 NC 0 Moore Machine: State Table Note: state S0 could be eliminated (S0 == S9), if S9 was start state! UAH-CPE/EE 422/522 AM

  14. Moore Machine Timing • X = 0010_1001 => Z = 1110_0011 Moore Mealy UAH-CPE/EE 422/522 AM

  15. S0 S2 S6 S7 S3 S1 S5 S4 State Assignments Guidelines to reduce the amount of combinational logic Rule I: (S0, S9, S10), (S4, S5), (S6, S7) Rule II: (S1, S2), (S3, S4), (S4, S5), (S6, S7), (S7, S8), (S9, S10) Rule III: (S0, S2, S4, S6, S8, S9)(S1, S3, S5, S7, S10) Q1Q2 01 10 00 11 Q3Q4 s10 S8 S9 00 S0 – 0010 S1 - 0111 …. S10 - 0100 01 11 10 UAH-CPE/EE 422/522 AM

  16. Moore Machine: Another Example A Converter for Serial Data Transmission: NRZ-to-Manchester • Coding schemes for serial data transmission • NRZ: nonreturn-to-zero • NRZI: nonreturn-to-zero-inverted • 0 in input sequence – the bit transmitted is the same as the previous bit; • 1 in input sequence – transmit the complement of the previous bit • RZ: return-to-zero • 0 – 0 for full bit time; 1 – 1 for the first half, 0 for the second half • Manchester UAH-CPE/EE 422/522 AM

  17. Moore Network for NRZ-to-Manchester UAH-CPE/EE 422/522 AM

  18. Moore Network for NRZ-to-Manchester UAH-CPE/EE 422/522 AM

  19. Synchronous Design • Use a clock to synchronize the operation of all flip-flops, registers, and counters in the system • all changes occur immediately following the active clock edge • clock period must be long enough so that all changes flip-flops, registers, counters will have time to stabilize before the next active clock edge • Typical design: Control section + Data Section Data registersArithmetic Units Counters Buses, Muxes, … Sequential machineto generate control signals to control the operation of data section UAH-CPE/EE 422/522 AM

  20. Data section // s= n*(n+a) // R1=n, R2=a // R1=s Design flowchart for SMUL operation Design Control section S0 S1 F 0 0 B 0 1 B – C0 1 0 B + C0 1 1 A + B An Example UAH-CPE/EE 422/522 AM

  21. Timing Chart for System with Falling-edge Devices UAH-CPE/EE 422/522 AM

  22. Timing Chart for System with Rising-edge Devices UAH-CPE/EE 422/522 AM

  23. Principles of Synchronous Design • Method • All clock inputs to flip-flops, registers, counters, etc.,are driven directly from the system clock or from the clock ANDed with a control signal • Result • All state changes occur immediately following the active edge of the clock signal • Advantage • All switching transients, switching noise, etc., occur between the clock pulses and have no effect on system performance UAH-CPE/EE 422/522 AM

  24. Asynchronous Design • Disadvantage - More difficult • Problems • Race conditions: final state depends on the order in which variables change • Hazards • Special design techniques are needed to cope with races and hazards • Advantages = Disadvantages of Synchronous Design • In high-speed synchronous design propagation delay in wiring is significant => clock signal must be carefully routed so that it reaches all devices at essentially same time • Inputs are not synchronous with the clock – need for synchronizers • Clock cycle is determined by the worst-case delay UAH-CPE/EE 422/522 AM

  25. To Do • Read • Textbook chapters 1.6, 1.7, 1.8, 1.10, 1.11, 1.12 UAH-CPE/EE 422/522 AM

  26. Equivalent States • Two state are equivalent if we cannot tell them apart by observing input and output sequences Definition: Two states are equivalent si==sj only and only if, for every input sequence X, the output sequences Z1 and Z2 are the same. Not practical => try all sequences (what is the length of sequence?) UAH-CPE/EE 422/522 AM

  27. Equivalent States State Equivalence Theorem • Two state are equivalent Si == Sj if and only if for every single input X, the outputs are the same and the next states are equivalent UAH-CPE/EE 422/522 AM

  28. State Table Reduction • States a and h have the same next states and outputs (when X=0 and X=1) • Eliminate h from the table and replace with a • States a and b have the same output =>they are same iff c==d and f==e. We say c-d and e-f are implied pairs for a-b.To keep track of the implied pairs we make an implication chart. UAH-CPE/EE 422/522 AM

  29. State Table Reduction • Make another pass through the chart.E-g cell contains c-e and b-g; since c-e cell contains x, c!=e => e!=g (put X). • Repeat the step 4 until no additional squares are X-ed. {Put X in f-g, a-c, a-d, b-c, b-d squares}. • The remaining squares indicate equivalent state pairs => a==b, c==d, e==f. UAH-CPE/EE 422/522 AM

  30. State Table Reduction UAH-CPE/EE 422/522 AM

  31. Implication Table Method • 1. Construct a chart that contains a square for each pair of states. • 2. Compare each pair in the state table. If the outputs associated with states i and j are different, place an X in square i-j to indicate that i!=j.If outputs are the same, place the implied pairs in square i-j. If outputs and next states are the same (or i-j implies only itself), i==j. • 3. Go through the implication table square by square. If square i-j contains the implied pair m-n, and square m-n contains X, then i!=j, and place X in square i-j. • 4. If any Xs were added in step 3, repeat step 3 until no more Xs are added. • 5. For each square i-j that does not contain an X, i==j. UAH-CPE/EE 422/522 AM

  32. Intro to VHDL • Technology trends • 1 billion transistor chip running at 20 GHz in 2007 • Need for Hardware Description Languages • Systems become more complex • Design at the gate and flip-flop level becomes very tedious and time consuming • HDLs allow • Design and debugging at a higher level before conversion to the gate and flip-flop level • Tools for synthesis do the conversion • VHDL, Verilog • VHDL – VHSIC Hardware Description Language UAH-CPE/EE 422/522 AM

  33. Intro to VHDL • Developed originally by DARPA • for specifying digital systems • International IEEE standard (IEEE 1076-1993) • Hardware Description, Simulation, Synthesis • Provides a mechanism for digital design and reusable design documentation • Support different description levels • Structural (specifying interconnections of the gates), • Dataflow (specifying logic equations), and • Behavioral (specifying behavior) • Top-down, Technology Dependent UAH-CPE/EE 422/522 AM

  34. VHDL Description of Combinational Networks UAH-CPE/EE 422/522 AM

  35. Entity-Architecture Pair Full Adder Example UAH-CPE/EE 422/522 AM

  36. VHDL Program Structure UAH-CPE/EE 422/522 AM

  37. 4-bit Adder UAH-CPE/EE 422/522 AM

  38. 4-bit Adder (cont’d) UAH-CPE/EE 422/522 AM

  39. 4-bit Adder - Simulation UAH-CPE/EE 422/522 AM

  40. Modeling Flip-Flops Using VHDL Processes • Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time General form of process UAH-CPE/EE 422/522 AM

  41. Concurrent Statements vs. Process A, B, C, D are integers A=1, B=2, C=3, D=0 D changes to 4 at time 10 Simulation Results time delta A B C D 0 +0 0 1 2 0 • +0 1 2 3 4 (stat. 3 exe.) 10 +1 1 2 4 4 (stat. 2 exe.) • +2 1 4 4 4 (stat. 1 exe.) 10 +3 4 4 4 4 (no exec.) UAH-CPE/EE 422/522 AM

  42. D Flip-flop Model Bit values are enclosed in single quotes UAH-CPE/EE 422/522 AM

  43. JK Flip-Flop Model UAH-CPE/EE 422/522 AM

  44. JK Flip-Flop Model UAH-CPE/EE 422/522 AM

  45. Using Nested IFs and ELSEIFs UAH-CPE/EE 422/522 AM

  46. VHDL Models for a MUX Sel represents the integerequivalent of a 2-bit binary number with bits A and B If a MUX model is used inside a process, the MUX can be modeled using a CASE statement(cannot use a concurrent statement): UAH-CPE/EE 422/522 AM

  47. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic); end SELECTOR; architecture RTL1 of SELECTOR is begin p0 : process (A, SEL) begin if (SEL = "0000") then Y <= A(0); elsif (SEL = "0001") then Y <= A(1); elsif (SEL = "0010") then Y <= A(2); elsif (SEL = "0011") then Y <= A(3); elsif (SEL = "0100") then Y <= A(4); elsif (SEL = "0101") then Y <= A(5); elsif (SEL = "0110") then Y <= A(6); elsif (SEL = "0111") then Y <= A(7); elsif (SEL = "1000") then Y <= A(8); elsif (SEL = "1001") then Y <= A(9); elsif (SEL = "1010") then Y <= A(10); elsif (SEL = "1011") then Y <= A(11); elsif (SEL = "1100") then Y <= A(12); elsif (SEL = "1101") then Y <= A(13); elsif (SEL = "1110") then Y <= A(14); else Y <= A(15); end if; end process; end RTL1; MUX Models (1) UAH-CPE/EE 422/522 AM

  48. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic); end SELECTOR; architecture RTL3 of SELECTOR is begin with SEL select Y <= A(0) when "0000", A(1) when "0001", A(2) when "0010", A(3) when "0011", A(4) when "0100", A(5) when "0101", A(6) when "0110", A(7) when "0111", A(8) when "1000", A(9) when "1001", A(10) when "1010", A(11) when "1011", A(12) when "1100", A(13) when "1101", A(14) when "1110", A(15) when others; end RTL3; MUX Models (2) UAH-CPE/EE 422/522 AM

  49. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic); end SELECTOR; architecture RTL2 of SELECTOR is begin p1 : process (A, SEL) begin case SEL is when "0000" => Y <= A(0); when "0001" => Y <= A(1); when "0010" => Y <= A(2); when "0011" => Y <= A(3); when "0100" => Y <= A(4); when "0101" => Y <= A(5); when "0110" => Y <= A(6); when "0111" => Y <= A(7); when "1000" => Y <= A(8); when "1001" => Y <= A(9); when "1010" => Y <= A(10); when "1011" => Y <= A(11); when "1100" => Y <= A(12); when "1101" => Y <= A(13); when "1110" => Y <= A(14); when others => Y <= A(15); end case; end process; end RTL2; MUX Models (3) UAH-CPE/EE 422/522 AM

  50. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic); end SELECTOR; architecture RTL4 of SELECTOR is begin Y <= A(conv_integer(SEL)); end RTL4; MUX Models (4) UAH-CPE/EE 422/522 AM

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