Report on the progress of the 40MHz SEU Test System based on DE2 Board

1. Report on the progress of the 40MHz SEU Test System based on DE2 Board 20 Jan. 2010 in CPPM Zhao Lei

2. Index of Content • System Description • Architecture of Logic in FPGA Basic description Test mode and time sequence Synchronization of the read back data Data Acquisition and Storage • Architecture of Software with GUI (Graphic User Interface) • Test Results Output clock for SEU chip of different frequency Output signal sequence of the FPGA for 4 test modes Function of testing cable delay Format of files saved on the disk • Consideration on Signal Integrity of the system • Conclusion

3. Test System Description

4. Architecture of Logic in FPGA

5. Basic structure of the SEU chip under test Triple Redundancy Latches

6. 4 Test Modes for this SEU Test System

7. Signal Sequence for Test Mode 0-- static test without read back

8. Signal Sequence for Test Mode 1-- static test with read back

9. Signal Sequence for Test Mode 2-- SEU Test versus frequency based on latches

10. Signal Sequence for Test Mode 3-- SEU Test versus frequency based on DFFs

11. Synchronization of the read back data

12. Synchronization of the read back data Delay between the clock and output data from the SEU chi signal sequence generated to test the delay

13. Data Acquisition and Storage

14. Architecture of Software with GUI (Graphic User Interface)

15. Configuration Panel Command Panel Information Display Panel Graphic User Interface Status Panel

16. Basic sequence of each test process

17. Test Results--Output clock for SEU chip of different frequency

18. Test Results--Output clock for SEU chip of different frequency

19. Test Results--Output clock for SEU chip of different frequency

20. Test Results--Output clock for SEU chip of different frequency

21. Output signal sequence of the FPGA for Test Mod 0 at 40 MHz -- Beam signal -- ‘Load’ signal for SEU chip -- ‘Readback’ signal for SEU chip -- ‘Clock’ signal for SEU chip

22. Output signal sequence of the FPGA for Test Mod 1 at 40 MHz -- Beam signal -- ‘Load’ signal for SEU chip -- ‘Readback’ signal for SEU chip -- ‘Clock’ signal for SEU chip

23. Output signal sequence of the FPGA for Test Mod 2 at 40 MHz -- Beam signal -- ‘Load’ signal for SEU chip -- ‘Readback’ signal for SEU chip -- ‘Clock’ signal for SEU chip

24. Output signal sequence of the FPGA for Test Mod 3 at 40 MHz -- Beam signal -- ‘Clock’ signal for SEU chip -- Read back data from SEU chip

25. Function of testing cable delay 600 kHz 10 MHz 40 MHz

26. Format of files saved on the disk Test Mode 1 Test Mode 0

27. Format of files saved on the disk Test Mode 2 Test Mode 3

28. Consideration on Signal Integrity for the clock input of SEU chip Method of serial impedance match Waveform of clock with 10 MHz frequency, data “0000” Waveform of clock with 10 MHz frequency, data “1010”

29. Consideration on Signal Integrity for the clock input of SEU chip The new method for impedance match Waveform of clock with 40 MHz frequency, data “0000” Waveform of clock with 40 MHz frequency, data “1010”

30. Consideration on Signal Integrity for psout data from SEU chip Waveform of the ‘psout’ signal of Channel 5 Waveform of the ‘psout’ signal of Channel 6 Location of the psout signals and the clock

31. Conclusion • The logic in FPGA has been established to generate all necessary signals, acquire data and do corresponding data analysis. • The software could conduct the user’s commands and communicates well with the FPGA through the USB interface. • More should be considered about the signal integrity between the interface board and the SEU chip. • The essential modification in the hardware is to change the impedance match method and provide more shielding between important signals.

32. Advices on the modification concerning the Signal Integrity • 1) Change the impedance match method from serial impedance match to terminal impedance match. So 100 ohm resistors should be added near all the input pins of the SEU chip, including: resetb, serin, load, readback, parity_in, error_in, clock, selout. • 2) Change the VCC supply from 1.5 V to 3.3 V for Bank B of the TTL transceiver which drives the input signals to the SEU chip. And serial resistors of 120 ohm should be used to tune the amplitude of the signals at the input pins of the SEU chip. • 3) More wires should be used as for ground, which are used to shielding the important signals, such as clock, serin and psout. • 4) To provide enough margin between the output signal from SEU chip and the TTL transceiver input level, the VDD_LVDS and VDD1 and VDD2 should remain separated in new design. • 5) Add 'lvds_test_out' signal as for another method for the synchronization of read back data. • 6) The power supply of 3.3 V should be provided for the interface board to the SEU board. By the way, the report about the system is attached.

33. Thanks