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OTIS ( O uter Tracker T ime I nformation S ystem) A TDC for LHCb

OTIS ( O uter Tracker T ime I nformation S ystem) A TDC for LHCb. 8 th Workshop on Electronics for LHC Experiments September 9 – 13, 2002 Colmar, France OTIS Group, University Heidelberg: Harald Deppe Uwe Stange Ulrich Trunk Ulrich Uwer. Contents. Overview

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OTIS ( O uter Tracker T ime I nformation S ystem) A TDC for LHCb

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  1. OTIS (Outer Tracker Time Information System)A TDC for LHCb 8th Workshop on Electronics for LHC Experiments September 9 – 13, 2002 Colmar, France OTIS Group, University Heidelberg: Harald Deppe Uwe Stange Ulrich Trunk Ulrich Uwer

  2. Contents • Overview Outer Tracker, Front End Electronics & OTIS • OTIS Chip • Concept • Components of the OTIS Chip • OTIS1.0 Prototype Measurements • Summary

  3. Outer Tracker / FE • Drift time measurement • Mounting on detector • Approx. 50,000 channels • Data of 4 TDC (32 chan-nels each) gets serialised and transmitted optically (1.28GBit/s) 4 x 320MBit/s 9.6GBit/s • Chip Requirements:  1ns resolution (6 bit)  drift times of up to 50ns  40MHz, clock driven design  1.1MHz L0 trigger rate  up to 10% occupancy  4µs trigger latency  radiation hard design (pipeline length: 160)

  4. OTIS: Concept Components: • 32 maskable channels • DLL, HitRegister, PrePipeline: 6 bit drift time generation, playback data feed in • Pipeline, Derandomizing Buffer: Intermediate data storage, compensation of trigger rate fluctuations • Control Algorithm: Memory and trigger management, data output • Slow Control Interface: Programming the chips behaviour • DAC: ASD-Chip bias

  5. OTIS: DLL, HitReg, Decoder Delay Chain Vctrl Clock Charge pump Phase detector 64 Time bins ( 390ps nom. resolution) Hit Signal D Q D Q D Q 64 Hit registers Decoder 64:6 6 bit drift time

  6. OTIS: DLL, HitReg, Decoder Delay Chain Vctrl Clock Charge pump Phase detector 64 Time bins ( 390ps nom. resolution) Hit Signal D Q D Q D Q 64 Hit registers storing a picture of the Hit Signal: Time Decoder 64:6 0..01110 .. 0 6 bit drift time

  7. OTIS: DLL Prototype Vctrl /mV Dynamic Range • Results Dynamic range: Vctrl: 1V Lock range: flock: 29-56MHz @ 300K Tlock: 10-90°C @ 40MHz Lock time: tlock < 1µs Differential nonlinearity: DNL = 0,51 ± 0,03 LSB (190ps)

  8. OTIS: Pipeline, DBuffer • Realised as dual ported SRAM • (164 + 48) x 240Bit x 40MHz  1.1GByte/s  low power design • Test chip OTISMem1.0  fully functional  expected behaviour confirmed (operational up to 100MHz)

  9. OTIS: Control Algorithm • Management of memory, trigger and data output. • Verification of critical parts on FPGA. • Data format:  First hit out of 1, 2 or 3 BX  Single Hit TDC  8bit drift times  Independant from occupancy  Fixed read out length • Data format guarantees synchronous operation of all TDC

  10. OTIS: Data format (planned) • Data format for 1, 2 or 3 BX per trigger (programmable, truncatable to 900ns) • 1 BX per trigger (100% mean strip occupancy w/o truncation) • 2 BX per trigger (50% mean strip occupancy w/o truncation) • 3 BX per trigger (27% mean strip occupancy w/o truncation)

  11. Contents • Overview Outer Tracker, Front End Electronics & OTIS • OTIS Chip • Concept • Components of the OTIS Chip • OTIS1.0 Prototype Measurements • Summary

  12. OTIS1.0 Prototype • First prototype with basic functionality • ~700.000 transistors • 5100µm x 6000µm • Tape out: 15/04/2002 Delivery: 29/07/2002 • Small test PCB with possibility to connect ASD and GOL chips

  13. OTIS Under Test (1) • DLL Lock Time • Power Consumption • 185mA or 465mW after PowerUp reset • 220mA or 550mW operation @ 40MHz Ch1: Clock Ch2: notReset Ch3: Vctrl Vctrl 1.1V Tlock  1µs

  14. OTIS Under Test (2) • Read Out Sequence Debug Signals Sequence Start Sequence Stop Data (8bit) Header Drift time pattern • Correct memory and trigger management Correct frame length • Correct timing and behaviour of  Correct data encoding for debug signals - header - drift times

  15. OTIS Under Test (3) • Drift Time Measurement: • Unexpected behaviour of the encoded drift time: under study • Workaround to procede with test: double hit pre- charges the decoder preliminary preliminary

  16. Preliminary Status OTIS1.0

  17. Outlook • Further investigations concerning drift time encoding • Study more chips, performance tests, random trigger tests, ... • Operation with detector prototype • Commissioning of the read out chain including TTCrx

  18. Summary • OTIS TDC Chip: • 32 channel TDC, 6 Bit drift time resolution • 40MHz, clock driven architecture • 160 events deep pipeline • 1.1MHz trigger rate • radiation hard • Prototype OTIS1.0 at hand since 6 weeks: almost fully functional

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