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STUDENT CHIP-2006

STUDENT CHIP-2006. DESIGN OF 16*16 BIT MULTIPLIER USING CARRY SAVE ADDER – Generation of partial products RCA CLA - Generation of final product(optional). Second Meeting. PRESENTATION OUTLINE. Why carry look ahead?

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STUDENT CHIP-2006

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  1. STUDENT CHIP-2006 DESIGN OF 16*16 BIT MULTIPLIER USING CARRY SAVE ADDER –Generation of partial products RCA CLA -Generation of final product(optional) Second Meeting

  2. PRESENTATION OUTLINE • Why carry look ahead? • Problems while executing the code in xilinx. • Synopsys-UMC18 results for multiplier-RCA. • Optimization of synopsys parameters such as speed(frq),power etc.. • Goals to be achieved for next meeting. • Vote of thanx.

  3. WHY CARRY LOOK AHEAD ADDER? • To improve the speed. • How much faster is this? • For a 4-bit adder, not much. There are 4 gates in the longest path of a carry lookahead adder, versus 9 gates for a ripple carry adder. • But if we do the cascading properly, a 16-bit carry lookahead adder could have only 8 gates in the longest path, as opposed to 33 for a ripple carry adder. • Newer CPUs these days use 64-bit adders. That’s 12 vs. 129 gates! • The delay of a carry lookahead adder grows logarithmically with the size of the adder, while a ripple carry adder’s delay grows linearly. • The thing to remember about this is the trade-off between complexity and performance. Ripple carry adders are simpler, but slower. Carry lookahead adders are faster but more complex.

  4. Errors while simulating VHDL code for CLA • Some logical errors found in synthesis report • # Time: 510 ns Iteration: 0 Instance: /mul_tb • # ERROR: 510000 ps: Bad result for 2C96 * 4276 = 0B933924, obtained: 0B4B3924 • # ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE • # Time: 570 ns Iteration: 0 Instance: /mul_tb • # ERROR: 570000 ps: Bad result for F12D * E0E0 = D3DA6760, obtained: 1A3B6760 • # ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE • # Time: 630 ns Iteration: 0 Instance: /mul_tb • # ERROR: 630000 ps: Bad result for 88C2 * CADC = 6C5E9AB8, obtained: 27FD9AB8 • # ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE • # Time: 690 ns Iteration: 0 Instance: /mul_tb • # ERROR: 690000 ps: Bad result for 5025 * 6A74 = 2153A2C4, obtained: 1953A2C4 • # ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE • # Time: 750 ns Iteration: 0 Instance: /mul_tb • # ERROR: 750000 ps: Bad result for FFFF * FFFF = FFFE0001, obtained: 00000001 • # ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE • # Time: 810 ns Iteration: 0 Instance: /mul_tb • # ERROR: 810000 ps: Bad result for 0000 * 0000 = 00000000, obtained: 00000000 • # ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE • # Time: 870 ns Iteration: 0 Instance: /mul_tb • # ERROR: 870000 ps: Bad result for 0000 * FFFF = 00000000, obtained: 00000000 • # ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE • # Time: 930 ns Iteration: 0 Instance: /mul_tb • # ERROR: 930000 ps: Bad result for FFFF * 0000 = 00000000, obtained: 00000000 • # • # TEST COMPLETED WITH ERRORS: 930000 ps • # SUMMARY: 14 error(s), 0 warning(s) and 0 note(s) • # ** Failure: Simulation terminated normally • # Time: 930 ns Iteration: 0 Process: /mul_tb/tester File: mul_tb.vhd • # Break at G:/chip/projekte/claa/syslog.vhd line 279 • # Simulation Breakpoint: Break at G:/chip/projekte/claa/syslog.vhd line 279 • # MACRO ./mul_tb.fdo PAUSED at line 15

  5. SYNOPSYS PARAMETERS • Parameters to be altered so as to achieve the desired goals are: • Speed • Power • Area • But the task that i was given is to achieve good performance i.e high speed • means design should have minimum delay. And for me(being CE student) the • only parameter that has to be altered so as to get the desired speed is frequency regardless of area and power... • Let us see the results when i used different frequencies in synopsys simulation.......

  6. SYNOPSYS-UMC18 RESULTS • Frequensy(MHz), DRT(ns), DAT(ns), Power(uw) • at 10 -13.75 - • at 100 9.94 -9.94 16.02 • at 150 6.60 -6.60 33.0097 • at 200 4.93 -5.58 54.19 • at 250 3.94 -5.78 88.46 • at 500 2.1 -5.78 120.23 • DRT Data required time • DAT Data arrival time

  7. OTHER PARAMETERS TO REDUCEGATE DELAYS • Every gate takes some small fraction of a second between the time inputs are presented and the time the correct answer appears on the outputs. This little fraction of a second is called a gate delay. • Forevision on: capacitances(load,junction,wire etc), Vth, power and devices(like CLA instead RCA adders). 1 x x’ 0 gate delays

  8. Vote of thanx • Thank you one and all • By Nagesh B. • CE-2nd sem

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