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RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan Brent Nelson and Brad Hutchings FPL September 5-7, 2011. Why Build Your Own Tools Anyway?. Proof of concept in their own right

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RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

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  1. RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan Brent Nelson and Brad Hutchings FPL September 5-7, 2011

  2. Why Build Your Own Tools Anyway? • Proof of concept in their own right • Hypothetical architectures may not account for all real-world factors • Targeting real chips important • The field needs wild and crazy ideas • The vendors don’t have all the answers! • That requires custom CAD tools

  3. The Challenge • Building custom physical CAD Tools for commercial FPGAs == difficult • Closed, proprietary device databases • Unsupported interfaces • Architectural nuances complicate things…

  4. Motivation #1: Rapid Prototyping quality of result (QOR) hours minutes seconds tool runtime

  5. Motivation #1: Rapid Prototyping quality of result (QOR) Commercial toolsfocus here… hours minutes seconds tool runtime

  6. Motivation #1: Rapid Prototyping For rapid prototyping and implementation we would like tools which focus here… quality of result (QOR) Commercial toolsfocus here… hours minutes seconds tool runtime

  7. Motivation #2: Reliability • SEU mitigation using TMR • Selective duplication tools • Single-bit TMR failures in routing • Half-latch detection • Weak keeper tie-offs susceptible to SEUs • Need a way to do post-PAR analysis • Need a way to do post-PAR modifications

  8. XDL: A Physical Database for Xilinx • A textual design database representation • For Xilinx designs • Available for many years Custom CAD Tools

  9. #1: XDL as a Design Representation • xdl –ncd2xdl design • Converts NCD to XDL • xdl –xdl2ncd design • Converts XDL back to NCD • Can inject own CAD tools at any point in the flow or bypass it entirely • Must convert back to NCD for bitgen Custom CAD Tools

  10. #2: XDLRC as a Device Description • xdl -report -pips -all_conns partName • Dumps textual description of specific device as a .xdlrc file • Details everything you need to write placers and routers (except timing data)

  11. Challenges of XDLRC Device Descriptions • They are massive! • Up to 73GB of text for one device! • Difficult for tools to directly operate on XDLRC • They are missing some information • Primitive sites that support more than 1 type • Pin name mappings missing for some sites • Result: placement/routing inefficiencies occur • RapidSmith solves these problems

  12. Some Terminology

  13. A Familiar View of the Fabric…

  14. A Familiar View of the Fabric…

  15. A Familiar View of the Fabric… L_TERM INT INT_SO IOIS INT CLB INT CLB INT L_TERM INT INT_SO INT INT IOIS CLB CLB INT L_TERM INT INT_SO IOIS INT CLB INT CLB INT

  16. XDLRC Abstraction – 2D Tile Array

  17. XDLRC Abstraction - Tiles HCLK_X1Y39 INT_X2Y37 CLB_X2Y37 DSP_X10Y32 BRAM_X5Y32

  18. XDLRC Abstraction – Primitive Sites INT_X2Y37 Contains: TIEOFF_X2Y37 CLB_X2Y37 Contains: SLICE_X3Y75 SLICE_X3Y74 SLICE_X2Y75 SLICE_X2Y74 DSP_X10Y32 Contains: DSP48_X0Y17 DSP48_X0Y16 BRAM_X5Y32 Contains: RAMB16_X0Y8 FIFO16_X0Y8

  19. XDL Examples

  20. XDL Example inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91 , cfg " BXINV::BX BYINV::#OFF ... F:inst23lut0:#LUT:D=((~A1*A3)+(A1*A2)) G:inst23lut1:#LUT:D=((~A1*A3)+(A1*A4)) ... YUSED::#OFF "; ... net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , ;

  21. XDL Example inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91 , cfg " BXINV::BX BYINV::#OFF ... F:inst23lut0:#LUT:D=((~A1*A3)+(A1*A2)) G:inst23lut1:#LUT:D=((~A1*A3)+(A1*A4)) ... YUSED::#OFF "; ... net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , pip CLB_X31Y53 IMUX_B18_INT -> G3_PINWIRE2 , pip CLB_X31Y54 YQ_PINWIRE2 -> SECONDARY_LOGIC_OUTS6_INT , pip INT_X31Y53 OMUX_S3 -> IMUX_B18 , pip INT_X31Y54 SECONDARY_LOGIC_OUTS6 -> OMUX3 , ;

  22. XDL Module Example module "mux" "inst23" , cfg " _SYSTEM_MACRO::FALSE "; port "mux5i_0_inport" "inst31" "F4"; port "mux5i_1_inport" "inst33" "F2"; ... inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91 , cfg " BXINV::BX BYINV::#OFF ... YUSED::#OFF "; ... net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , pip CLB_X31Y53 IMUX_B18_INT -> G3_PINWIRE2 , pip CLB_X31Y54 YQ_PINWIRE2 -> SECONDARY_LOGIC_OUTS6_INT , pip INT_X31Y53 OMUX_S3 -> IMUX_B18 , pip INT_X31Y54 SECONDARY_LOGIC_OUTS6 -> OMUX3 , ; endmodule "mux";

  23. The RapidSmith Tool Suite

  24. RapidSmith XDLFile RapidSmith XDLFile

  25. RapidSmith XDLFile RapidSmith Internal GraphRepresenation JavaAPI XDLFile

  26. RapidSmith XDLFile RapidSmith CustomCad Tools ( create, place,route, modify circuits ) Internal GraphRepresenation JavaAPI XDLFile

  27. RapidSmith Abstractions XDLRC XDL

  28. XDLRC Device File Creation • Three major strategies to reduce XDLRC information size: • Aggressive wire and object reuse • Careful pruning of unnecessary wires • Customized serialization and compression • XDLRC size compression of >10,000X • Device files load in just a few seconds or less

  29. RapidSmith Device Files Performance

  30. 7 ExampleS of RapidSmith USE and Capabilities

  31. RapidSmith Example #1: Random Placer • publicclass RandomPlacer{ • publicstaticvoid main(String[] args){ • // Create and load a design • Design design = newDesign(args[0]); • Random rng = newRandom(0); // Create random number generator • // Place all unplaced instances • for(Instance i : design.getInstances()){ • if(i.isPlaced())continue; • PrimitiveSite[] sites = • design.getDevice().getAllCompatibleSites(i.getType()); • intidx = rng.nextInt(sites.length); • intwatchDog = 0; • // Find a free primitive site • while(design.isPrimitiveSiteUsed(sites[idx])){ • if(++idx > sites.length) idx = 0; • if(++watchDog > sites.length) • System.out.println("Placement failed."); • } • i.place(sites[idx]); • } • // Save the placed design • design.saveXDLFile(args[1]); • } • }

  32. RapidSmith Example #2: Placing a Module // Load XDL file (parses XDL, populated design object) Design design = newDesign("moduleContainingDesign.xdl"); // Get the 1024-FFT module definition by name Module fft = design.getModule("fft1024"); // Create an instance of the FFT module called "f0" ModuleInstance mi = design.createModuleInstance("f0", fft); //Find all compatible sites with the anchor PrimitiveType type = mi.getAnchor().getType(); PrimitiveSite[] sites = design.getDevice().getAllCompatibleSites(type); inti = 0; while(!mi.place(sites[i++], design.getDevice())){ if(i >= sites.length) error(mi.getName()+ " has no valid placement!"); }

  33. RapidSmith Example #3: VCC/GND Handling • GND/VCC supplied in two ways: • LUTs configured to drive ‘1’ or ‘0’ • TIEOFF primitives in every switch box • Supplied GND / VCC posts • Router must partition nets into neighborhoods to use local static sources • RapidSmith includes a StaticSourceHandler class with a variety of methods to provide this functionality

  34. RapidSmith Example #4: HMFlow • Rapid compilation approach using hard macros • Built on top of RapidSmith Design Parser & Mapper Design Stitcher XDL Hard Macro Placer XDL Router .xdl .mdl Placed & Routed XDL Input Designs Part of CHREC research project Demonstrated > 50X reduction in tool flow time HM Cache Generic HMG Hard Macro Sources

  35. RapidSmith Example #5: Device Browser

  36. RapidSmith Example #6: Design Explorer

  37. RapidSmith Example #7: Custom Hard Macro Placer

  38. RapidSmith Example #7: Timing Visualizer

  39. Conclusion • RapidSmith • Provides XDL-based infrastructure • Designed to aid in the construction of custom CAD tools • Flexible • Custom CAD flow • HMFlow for Hard Macro-Based Design • Custom individual steps in the flow • Placer or router • Post Xilinx flow circuit modifications • Reliability modifications • Post Xilinx flow circuit analysis • Timing visualization • Available open source: • http://rapidsmith.sourceforge.net

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