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Wire Length Prediction-based Technology Mapping and Fanout Optimization. Qinghua Liu Malgorzata Marek-Sadowska VLSI Design Automation Lab UC-Santa Barbara. Outline. Motivation and previous work Pre-layout wire length prediction Technology mapping with wire-length prediction
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Wire Length Prediction-based Technology Mapping and Fanout Optimization Qinghua Liu Malgorzata Marek-Sadowska VLSI Design Automation Lab UC-Santa Barbara
Outline • Motivation and previous work • Pre-layout wire length prediction • Technology mapping with wire-length prediction • Fanout optimization with wire-length prediction • Experimental results • Conclusions and future work
Motivation • Traditional logic synthesis does not consider accurate layout information • Placement quality depends on • netlist structure • placement algorithm
Previous work • Logic and physical co-synthesis • Layout-driven logic synthesis • Local netlist transformations • Metric-driven structural logic synthesis • Adhesion • Distance
Pre-layout wire-length prediction • Previous work • Statistical wire-length prediction • Lou Sheffer et al. “Why Interconnect Prediction Doesn’t work?” SLIP’00 • Individual wire-length prediction • Qinghua Liu et al. “Wire Length Prediction in Constraint Driven Placement” SLIP’03 • Semi-individual wire-length prediction • Predict that nets have a tendency to be long or short • Qinghua Liu et al. “Pre-layout Wire Length and Congestion Estimation” DAC’04
Summary of the semi-individual wire length prediction technique • Predict lengths of connections • Mutual contraction • Predict lengths of multi-pin nets by • Net range
Mutual contraction B.Hu and M.Marek-Sadowska, “Wire length prediction based clustering and its application in placement” DAC’03 v y u x
Relative weight of a connection v Wr(u, v) = 0.71 u EQ1 y EQ2 Wr(x, y) = 0.5 x
Mutual contraction of a connection Cp(x, y) = Wr(x, y) Wr(y, x) EQ3 Wr(u, v) = 0.71 Wr(v, u) = 0.33 Cp(u, v) = 0.234 Wr(x, y) = 0.71 Wr(y, x) = 0.6 Cp(x, y) = 0.426 v y j i u x
Predictions on connections (a) (b) Mutual contraction vs. Connection length
Net range 0 1 2 3 4 5 6 7 8 9 10 11 Circuit depth Example of net range
Predictions on multi-pin nets Net range vs. average length for multi-pin nets
Technology mapping with wire-length prediction (WP-Map) • Node Decomposition • Technology Mapping
Node decomposition a b c a G b c a b c T.Kutzschebauch and L.Stok, “Congestion aware layout driven logic synthesis”, ICCAD’01
CurrentPinNum>2? Greedy node decomposition algorithm CurrentPinNum=n N Done CurrentPinNum= CurrentPinNum-1 Y (n1,n2)=two input nets with largest mutual contraction Update mutual contraction Decompose(G,n1,n2) Remove n1 and n2, insert new net Decompose n-input gate G with wire length prediction
Correlation between mutual contraction and interconnection complexity Average mutual contraction vs. Rent’s exponent
Fanout optimization with wire-length prediction (WP-Fanout) • Net selection • Select all large-degree nets • Select small-degree nets with large net range • Net decomposition LT-tree Balanced tree Circuit depth
Experiment setting • LGSyn93 benchmark suite • Optimized by script.rugged • Mapped with 0.13um industrial standard cell library • Placement is done by mPL4 • Global routing is done by Labyrinth
Experimental results • Compare with the traditional area-driven technology mapping algorithm implemented in SIS • Results of the WP-Map algorithm • Results of combined WP-Map and WP-Fanout algorithm
Compare WP-Map with SIS Compare mapped netlists
Compare WP-Map with SIS (cont.) Average cut number distribution of C6288
Compare WP-Map with SIS (cont.) Results after placement and global routing
Compare WP-Map + WP-Fanout with SIS Results after placement and global routing
Conclusions • Wire length can be predicted in structural level • Mutual contraction • Net range • Wire length prediction technique can be applied into technology mapping and fanout optimization • 8.7% improvement on average congestion • 17.2% improvement on peak congestion
Future work • Logic extraction with wire-length and congestion prediction • Timing-driven technology mapping with wire-length prediction