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Board I/O

Board I/O. EE138 – SJSU. Objectives. Introducing board I/O Discussing differences between serial and parallel I/O Introducing interfacing to I/O Discussing I/O performance. Von Neumann-based I/O.

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Board I/O

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  1. Board I/O EE138 – SJSU

  2. Objectives • Introducing board I/O • Discussing differences between serial and parallel I/O • Introducing interfacing to I/O • Discussing I/O performance

  3. Von Neumann-based I/O I/O components on board are responsible for moving information into and out of the board to I/O devices connected to an embedded system.

  4. Board I/O Components Because I/O devices are so varied, ranging from simple circuits to other complete embedded systems, board I/O components can fall under one or more of several different categories, the most common including: • Networking and communications I/O • Input (keyboard, mouse, remote control, vocal, etc.) • Graphics and output I/O (touch screen, CRT, printers, LEDs, etc.) • Storage I/O (optical disk controllers, magnetic disk controllers, magnetic tape controllers, etc.) • Debugging I/O (BDM, JTAG, serial port, parallel port, etc.) • Real time and miscellaneous I/O (timers/counters, analog-to-digital converters and digital-to-analog converters, key switches, etc.)

  5. Ports and Device Controllers Board I/O can be as simple as basic circuit that connects master processor directly to a single I/O device, such as a master processor’s port to a clock or LED on board. A more complex I/O subsystem circuitry that includes several units as shown above

  6. Six Main Logical Units • Transmission medium:a wireless or wired medium connecting the I/O device tothe embedded board for data communication and exchanges • Communication port: what the transmission medium connects to on the board or, if a wireless system, what receives the wireless signal • Communication interface:which manages data communication between master CPU and I/O device or I/O controller, and is responsible for encoding data and decoding data to and from the logical level of an IC and the logical level of the I/O port. This interface can be integrated into the master processor, or can be a separate IC. • I/O controller:a slave processor that manages the I/O device • I/O buses:the connection between the board I/O and master processor • Master processor integrated I/O

  7. Examples of a Complex and a simple I/O Subsystem The I/O on a board can thus range from a complex combination of components, as shown in Figure 6-3a, to a few integrated I/O board components, as shown in Figure 6-3b. Figure 6-3b: Simple I/O Subsystem

  8. BASICS OF SERIAL COMMUNICATION Serial data communication uses two methods, asynchronous and synchronous. The synchronous method transfers a block of data (characters) at a time, whereas the asynchronous method transfers a single byte at a time.

  9. Asynchronous Serial Communication In the asynchronous method, each data character is placed between start and stop bits. This is called framing. The start bit is always a 0 (low) and one bit, but the stop bit(s) is 1 (high) and can be one or two bits. When there is no transfer, the signal is 1 (high), which is referred to as mark or iddle. Data D0 (LSB) goes first the rest of the bits until the MSB (D7). Example: the ASCII character “A” (8-bit binary 0100 0001) is framed between the start bit and a single stop bit.

  10. Example: a) Find the overhead due to framing when transmitting the ASCII letter “A” (01000001). b) Calculate the time it takes to transfer 10,000 characters as in question a) if we use 9600 bps. What percentage of time is wasted due to overhead? Solutions: a) 2 bits (one for the start bit and one for the stop bit). Therefore, for each 8-bit character, a total of 10 bits is transferred. b) 10,000 × 10 = 100,000 total bits transmitted. 100,000 / 9600 = 10.4 seconds; 2 / 10 = 20%.

  11. Baud Rate in the AVR In the AVR microcontroller five registers are associated with the USART. They are UDR (USART Data Register), UCSRA, UCSRB, UCSRC (USART Control Status Register), and UBRR (USART Baud Rate Register). Desired Baud Rate = Fosc/ (16(X + 1)) where X is the value we load into the UBRR register. To get the X value for different baud rates we can solve the equation as follows: X = (Fosc/ (16(Desired Baud Rate))) – 1 Assuming that Fosc = 8 MHz, we have the following: Desired Baud Rate = Fosc/ (16(X + 1)) = 8 MHz/16(X + 1) = 500 kHz/(X + 1) X = (500 kHz/ Desired Baud Rate) – 1

  12. Examples: 1) Find Baud Rate if UBRR = 67H = 103 Solution: Desired Baud Rate = Fosc/(16(X + 1)) = 8MHz/(16(103+1)) = 4807 bps 2) Find the UBRR value needed to have the following baud rates: (a) 9600 (b) 1200 for Fosc= 8 MHz. Solution: Fosc = 8 MHz => X = (8 MHz/16(Desired Baud Rate)) – 1 => X = (500 kHz/(Desired Baud Rate)) – 1 (a) (500 kHz/ 9600) – 1 = 52.08 – 1 = 51.08 = 51 = 33 (hex) is loaded into UBRR (b) (500 kHz/ 1200) – 1 = 416.66 – 1 = 415.66 = 415 = 19F (hex) is loaded into UBRR

  13. Baud Rate Generation Block Diagram Doubling the baud rate in the AVR There are two ways to increase the baud rate of data transfer in the AVR: 1. Use a higher-frequency crystal (not feasible in many cases). 2. Change a bit in the UCSRA register(U2X = 1). Desired Baud Rate = Fosc / (8 (X + 1)) when U2x = 1

  14. Baud Rate Error Calculation In calculating the baud rate we have used the integer number for the UBRR register values because AVR microcontrollers can only use integer values. By dropping the decimal portion of the calculated values we run the risk of introducing error into the baud rate. One way to calculate this error Error = (Calculated value for the UBRR – Integer part) / Integer part For example, with XTAL = 8 MHz and U2X = 0 we have the following for the 9600 baud rate: UBRR value = (500,000/ 9600) – 1 = 52.08 – 1 = 51.08 = 51 => Error = (51.08 – 51)/ 51 = 0.16%

  15. Examples: Given: XTAL = 7.3728 MHz. a) What value should be loaded into UBRR to have a 9600 baud rate for U2X = 0, 1? Give the answers in both decimal and hex. b) What are the baud rate errors in a)? Solutions: U2X = 0: (Fosc/16(baud rate)) – 1 = (7372800/16(9600)) – 1 = 47or 2FH U2X = 1: (Fosc/8(baud rate)) – 1 = (7372800 / 8 (9600)) – 1 = 94 or 2FH b) 0%

  16. Serial I/O - Board I/O that can transmit and receive data in serial in which data (characters) are stored, transferred and received one bit at a time. - Serial communication includes within its I/O subsystem a serial port and a serial interface. Serial interfaces manage the serial data transmission and reception between the master CPU and either the I/O device or its controller - Data can be transmitted between two devices in one of three directions: 1) Simplex scheme is when data stream can only be transmitted—and thus received—in one direction (see Figure 6-4a). 2) Half duplex scheme is when data stream can be transmitted and received in either direction, but in only one direction at any one time (see Figure 6-4b). 3) Full duplex scheme is when a data stream can be transmitted and received in either direction simultaneously (see Figure 6-4c).

  17. Serial I/O: Asynchronous • Data being transmitted is typically stored and modified within a serial interface’s transmission buffer. • The serial interface at the transmitter divides the data stream into groups, called packets, that typically range from either 4 to 8 bits per character or 5 to 9 bits per character. • Each of these packets is then encapsulated in frames to be transmitted separately. • The frames are packets modified (before transmission) by the serial interface to include a START bit at the start of the stream, and a STOP bit or bits. • Within the frame, after the data bits and before the STOP bit, a parity bit may also be appended. • Between the transmission of frames, the communication channel is kept in an idle state, meaning a logical level “1” or non-return to zero (NRZ) state is maintained.

  18. Serial I/O: Receiver • The serial interface of the receiver then receives frames by synchronizing to the START bit of a frame, delays for a brief period, and then shifts in bits, one at a time, into its receive buffer until reaching the STOP bit (s). • In order for asynchronous transmission to work, the bit rate (bandwidth) has to be synchronized in all serial interfaces involved in the communication. • Bit rate versus baud (symbol) rate: • If the system uses 1 bit per symbol (2 levels), then bit rate = symbol rate • If the system uses 2 bits per symbol (4 levels), then bit rate = 2 x symbol rate • If the system uses 3 bits per symbol (8 levels), then bit rate = 3 x symbol rate • Ex: UART (Universal Asynchronous Receiver Transmitter - learned in Lecture 4)

  19. Serial I/O: Synchronous • In a synchronous transmission, there are no START or STOP bits, and there is no idle period. • Data rates for receiving and transmitting must be in sync. • Synchronous transmission are synchronizing off of one common clock, which does not start and stop with each new frame. • On some boards, there may be an entirely separate clock line for the serial interface • In some synchronous serial interfaces, if there is no separate clock line, the clock signal may even be transmitted along with the data bits. • Ex: SPI

  20. Serial I/O Example: Networking and Communications: IEEE 802.11 Wireless LAN • 802.11-a to 802.11-n standards

  21. Serial I/O Example: Networking and Communications: IEEE 802.11 Wireless LAN (cont.) >>> As shown above, embedded boards need to either integrate 802.11 functionality as a slave controller or into the master chip, or the board needs to support one of the standard connectors for the other forms (PCI, PCMCIA, Compact Flash, etc.). On top of the 802.11 chipset integration, an embedded board design needs to take into consideration wireless LAN antenna placement and signal transmission requirements. The designer must ensure that there are no obstructions to prevent receiving and transmitting data.

  22. Cont. . When 802.11 is not integrated into the master CPU, such as with the System-on-Chip (SoC) shown above, the interface between the master CPU and the 802.11 board hardware also needs to be designed.

  23. Parallel I/O • Just as with serial I/O, parallel I/O hardware is also typically made up of some combination of six main logical units, except that the port is a parallel port and the communication interface is a parallel interface. The transmission medium, a wireless or wired medium connecting the I/O device to the embedded board for data communication and exchanges Communication port, what the transmission medium connects to on the board or, if a wireless system, what receives the wireless signal A communication interface, which manages data communication between master CPU and I/O device or I/O controller, and is responsible for encoding data and decoding data to and from the logical level of an IC and the logical level of the I/O port. This interface can be integrated into the master processor, or can be a separate IC. An I/O controller, a slave processor that manages the I/O device I/O buses, the connection between the board I/O and master processor The master processor integrated I/O

  24. Parallel I/O - Examples • Examples of board I/O that transfer and receive data in parallel include: • IEEE 1284 controllers (for printer/display I/O devices—see Example 3), • CRT ports • SCSI (for storage I/O devices). • Ethernet: A protocol that can potentially support both parallel and serial I/O (Example 4).

  25. Parallel I/O Example 3: “Parallel” Output and Graphics I/O

  26. Parallel I/O Example 3: “Parallel” Output and Graphics I/O • There are typically three logical components (engines) of I/O graphics on an embedded board: • The geometric engine, which is responsible for defining what an object is. Thisincludes implementing color models, an object’s physical geometry, material and lighting properties, and so on. • The rendering engine, which is responsible for capturing the description of objects. This includes providing functionality in support of geometric transformations, projections, drawing, mapping, shading, illumination, and so on. • The raster and display engine, which is responsible for physically displaying the object. It is in this engine that the output I/O hardware comes into play.

  27. Parallel I/O: Graphical Soft Copy vs. Hard Copy Display • An embedded system can output graphics via softcopy (video) or hardcopy (on paper) means. • The contents of the display pipeline differ according to whether the output I/O device outputs hard or soft graphics, so the display engine differs accordingly, as shown in Figures 6-15a and b above.

  28. NET+ARM50Embedded Board Parallel I/O • The IEEE 1284 specification defines a 40-signal port, but on the Net+ARM50 board, data and control signals are multiplexed to minimize the master processor’s pin count. • Aside from eight data signals DATA[8:1] (D0 – D7), IEEE 1284 control signals include: • PDIR, which is used for bidirectional modes and defines the direction of the external data transceiver. Its state is directly controlled by the BIDIR bit in the IEEE 1284 Control register (0 state, data is driven from the external transceiver towards 1285, the cable, and in the 1 state, data is received from the cable). • PIO, which is controlled by firmware. Its state is directly controlled by the PIO bit in the IEEE 1284 Control register. • LOOPBACK, which configures the port in external loopback mode and can be used to control the mux line in the external FCT646 devices (set to 1, the FCT646 transceivers drive inbound data from the input latch and not the real-time cable interface). Its state is directly controlled by the LOOP bit in the IEEE 1284 Control register. The LOOP strobe signal is responsible for writing outbound data into the inbound latch (completing the loop back path). The LOOP strobe signal is an inverted copy of the STROBE* signal. • STROBE* (nSTROBE), AUTOFD* (nAUTOFEED), INIT* (nINIT), HSELECT* (nSELECTIN), *ACK (nACK), BUSY, PE, PSELECT (SELECT), *FAULT (nERROR), …”

  29. Parallel and Serial I/O Example 4:Networking and Communications— Ethernet • One of the most widely implemented LAN protocols is Ethernet, which is primarily based upon the IEEE 802.3 family of standards. The hardware components can all be mapped to the physical layer of the OSI model. The firmware (software) required to enable Ethernet functionality maps to the lower section of the OSI data-link layer.

  30. Ethernet Components • Medium Attachment Unit (MAU) contains: • The MDI & the Physical Medium Attachment (PMA) • Attachment Unit Interface (AUI), carriesencoded signals between an MAU and the Ethernet interface in a processor. • The AUI is defined for up to 10 Mbps Ethernet devices, and specifies the connection between the MAU and the Physical Layer Signaling (PLS) sub layer (in terms of signal characteristics, connectors, cable length, etc.). • Ethernet interface • can exist on a master or slave processor, and contains the remaining Ethernet hardware and software components. • Physical Layer Signaling (PLS) component monitors the transmission medium, and provides a carrier sense signal to the Media Access Control (MAC) component.

  31. Ethernet Example 1: Pin Level From this paragraph, RJ-45 jack is the MDI, and the MC68160 enhanced Ethernet serial transceiver (EEST) is the MAU. On the MPC823, a 7-wire interface acts as the AUI. The SCC2 is the Ethernet interface, and “performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions

  32. Ethernet Example: Block Level & Chipset Level

  33. I/O Interface I/O hardware is made up master processor I/O, I/O controllers, a communications interface, a communication port, I/O buses, and a transmission medium

  34. I/O Interface

  35. Interfacing an I/O Controller and the Master CPU Four requirements: • An ability of the master CPU to initialize and monitor the I/O Controller. I/O controllers can typically be configured via control registers and monitored via status registers. • A way for the master processor to request I/O. The most common mechanisms used by the master processor to request I/O via the I/O controller are: • special I/O instructions (I/O mapped) in the ISA, and • memory-mapped I/O, in which the I/O controller registers have reserved spaces in main memory. • A way for the I/O device to contact the master CPU (e.g. interrupt) • Some mechanism for both to exchange data (e.g. DMA)

  36. I/O and Performance • I/O performance is one of the most important issues of an embedded design. I/O can negatively impact performance by bottlenecking the entire system. • Some of the most important shared features of I/O that can negatively impact board performance include: • The data rates of the I/O devices. • The speed of the master processor. • How to synchronize the speed of the master processor to the speeds of I/O. • How I/O and the master processor communicate. • I/O Performance • Throughput of the various I/O components • The execution time of an I/O component • The response time or delay time of an I/O component

  37. Summary • I/O subsystem was introduced as being some combination of • a transmission medium, • communication port, • a communication interface, • an I/O controller, • I/O buses, and • the master processor’s integrated I/O. • This chapter also discussed the integration of various I/O components within the subsystem to each other. • Networking schemes (RS-232, Ethernet, and IEEE 802.11) were provided as serial and parallel transmission I/O examples, as well as • a graphics example for parallel transmission. • This chapter also discussed the impact of board I/O on an embedded system’s performance.

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