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Digital Design – Hardware Description Languages

Digital Design – Hardware Description Languages. Chapter 9 - Hardware Description Languages. Digital Design Hardware Description Languages. Figure 9.1 Drawn circuit. Digital Design Hardware Description Languages.

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Digital Design – Hardware Description Languages

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  1. Digital Design – Hardware Description Languages Chapter 9 - Hardware Description Languages

  2. Digital DesignHardware Description Languages Figure 9.1 Drawn circuit.

  3. Digital DesignHardware Description Languages Figure 9.2 Schematics become hard to read beyond a dozen or so components -- the graphical information becomes a nuisance rather than an aid.

  4. Digital DesignHardware Description Languages Figure 9.3 Describing a circuit using a textual language rather than a graphical drawing: (a) schematic, (b) textual description in the English language.

  5. Digital DesignHardware Description Languages (VHDL) Figure 9.4 Describing a circuit using a textual language rather than a graphical drawing: (a) schematic, (b) textual description in the English language, (c) textual description in the VHDL language. Bolded words are reserved words in VHDL.

  6. Digital DesignHardware Description Languages (VHDL) Figure 9.7 Behavioral description of an OR gate.

  7. Digital DesignHardware Description Languages (VHDL) Figure 9.8 Behavioral description off DoorOpener design.

  8. library ieee; use ieee.std_logic_1164.all; entity Testbench is end Testbench; architecture behavior of Testbench is component DoorOpener port ( c, h, p: in std_logic; f: out std_logic ); end component ; signal c, h, p, f: std_logic; begin DoorOpener1: DoorOpener port map (c,h,p,f); process begin -- case 0 c <= ’0’; h <= ’0’; p <= ’0’; wait for 1 ns ; assert (f=’0’) report “Case 0 failed”; -- case 1 c <= ’0’; h <= ’0’; p <= ’1’; wait for 1 ns ; assert (f=’1’) report “Case 1 failed”; -- (cases 2-6 omitted from figure) -- case 7 c <= ’1’; h <= ’1’; p <= ’1’; wait for 1 ns ; assert (f=’0’) report “Case 7 failed”; wait ; -- process does not wake up again end process ; end behavior; Digital DesignHardware Description Languages (VHDL) Figure 9.9 Behavioral description of DoorOpener testbench.

  9. Digital DesignHardware Description Languages (VHDL) Figure 9.10 Behavioral description of a 4-bit register.

  10. Digital DesignHardware Description Languages (VHDL) Figure 9.11 Oscillator description.

  11. library ieee; use ieee.std_logic_1164.all; entity LaserTimer is port ( b: in std_logic; x: out std_logic; clk, rst: in std_logic ); end LaserTimer; architecture behavior of LaserTimer is type statetype is (S_Off, S_On1, S_On2, S_On3); signal currentstate, nextstate: statetype; begin statereg: process (clk, rst) begin if (rst=’1’) then currentstate <= S_Off; -- initial state elsif (clk=’1’ and clk’ event ) then currentstate <= nextstate; end if ; end process ; comblogic: process (currentstate, b) begin case currentstate is when S_Off => x <= ’0’; -- laser off if (b=’0’) then nextstate <= S_Off; elsif (b=’1’) then nextstate <= S_On1; end if ; when S_On1 => x <= ’1’; -- laser on nextstate <= S_On2; when S_On2 => x <= ’1’; -- laser still on nextstate <= S_On3; when S_On3 => x <= ’1’; -- laser still on nextstate <= S_Off; end case ; end process ; end behavior; Digital DesignHardware Description Languages (VHDL) Figure 9.12 Behavioral description of LaserTimer controller.

  12. Digital DesignHardware Description Languages (VHDL) Figure 9.13 Behavioral description of a full-adder.

  13. Digital DesignHardware Description Languages (VHDL) Figure 9.14 Structural description of a 4-bit carry-ripple adder.

  14. begin library ieee; Reg4_1: Reg4 port map (incC, tempC, clk, cnt); use ieee.std_logic_1164.all; Inc4_1: Inc4 port map (tempC, incC); AND4_1: AND4 port map (tempC(3), tempC(2) entity UpCounter is tempC(1), tempC(0), tc); port ( clk: in std_logic; cnt: in std_logic; outputC: process (tempC) C: out std_logic_vector(3 downto 0); begin tc: out std_logic C <= tempC ; ); end process ; end UpCounter; end structure; architecture structure of UpCounter is component Reg4 port ( I: in std_logic_vector(3 downto 0); Q: out std_logic_vector(3 downto 0); clk, ld: in std_logic ); end component; component Inc4 port ( a: in std_logic_vector(3 downto 0); s: out std_logic_vector(3 downto 0); ); end component; component AND4 port ( w,x,y,z: in std_logic; F: out std_logic ); end component; signal tempC: std_logic_vector(3 downto 0); signal incC: std_logic_vector(3 downto 0); Digital DesignHardware Description Languages (VHDL) Figure 9.15 Structural description of 4-bit up-counter.

  15. library ieee; use ieee.std_logic_1164.all; entity LaserDistMeasurer is port ( clk, rst: in std_logic; B, S: in std_logic; L: out std_logic; D: out std_logic_vector(15 downto 0) ); end LaserDistMeasurer; architecture structure of LaserDistMeasurer is component LDM_Controller port ( clk, rst: in std_logic; B, S: in std_logic; L: out std_logic; Dreg_clr, Dreg_ld: out std_logic; Dctr_clr, Dctr_cnt: out std_logic ); end component; component LDM_Datapath port ( clk: in std_logic; Dreg_clr, Dreg_ld: in std_logic; Dctr_clr, Dctr_cnt: in std_logic; D: out std_logic_vector(15 downto 0) ); end component ; signal Dreg_clr, Dreg_ld: std_logic; signal Dctr_clr, Dctr_cnt: std_logic; begin LDM_Controller_1: LDM_Controller port map (clk, rst, B, S, L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt); LDM_Datapath_1: LDM_Datapath port map (clk, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt, D); end structure; Digital DesignHardware Description Languages (VHDL) Figure 9.16 Structural description of top-level VHDL description of laser-based distance measurer.

  16. Digital DesignHardware Description Languages (VHDL) Figure 9.17 Structural description of the laser-based distance measurer’s datapath.

  17. Digital DesignHardware Description Languages (VHDL) case currentstate is library ieee; when S0 => use ieee.std_logic_1164.all; L <= ’0’; -- turn off laser Dreg_clr <= ’1’; -- clear Dreg entity LDM_Controller is nextstate <= S1; port ( clk, rst: in std_logic; when S1 => B, S: in std_logic; Dctr_clr <= ’1’; -- clear timer L: out std_logic; if (B=’1’) then Dreg_clr, Dreg_ld: out std_logic; nextstate <= S2; Dctr_clr, Dctr_cnt: out std_logic else ); nextstate <= S1; end LDM_Controller; end if ; when S2 => architecture behavior of LDM_Controller is L <= ’1’; -- turn on laser type statetype is (S0, S1, S2, S3, S4, S5); Dctr_cnt <= ’1’; -- enable timer signal currentstate, nextstate: statetype; nextstate <= S3; begin when S3 => statereg: process (clk, rst) L <= ’0’; -- turn off laser begin if (S=’1’) then if (rst=’1’) then nextstate <= S4; currentstate <= S0; -- initial state else elsif (clk=’1’ and clk’event) then nextstate <= S3; currentstate <= nextstate; end if ; end if ; when S4 => end process ; Dctr_cnt <= ’0’; -- disable timer comblogic: process (currentstate, B, S) nextstate <= S5; begin when S5 => L <= ’0’; Dreg_ld <= ’1’; -- load Dreg Dreg_clr <= ’0’; nextstate <= S1; Dreg_ld <= ’0’; end case ; Dctr_clr <= ’0’; end process ; Dctr_clr <= ’0’; end behavior ; Figure 9.18/9.19 Behavioral description of laser-based distance measurer’s controller.

  18. Digital DesignHardware Description Languages (Verilog) Figure 9.5 Describing a circuit using a textual language rather than a graphical drawing: (a) schematic, (b) textual description in the English language, (c) textual description in the Verilog language. Bolded words are reserved words in Verilog.

  19. Digital DesignHardware Description Languages (SystemC) Figure 9.6 Describing a circuit using a textual language rather than a graphical drawing: (a) schematic, (b) textual description in the English language, (c) textual description in the SystemC language. Bolded words are reserved words in SystemC.

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