Basic Logic Design with Verilog - Hardware Description Language

1. Basic Logic Design with Verilog- Hardware Description Language ESA Lab. MS. Student, Suknam Kwon

2. Contents • The Verilog Language • NC-Verilog Simulation • Design Synthesis • Summary ESA Laboratory

3. The Verilog Language

4. What is HDL/Verilog • Why use HDL (Hardware Description Language)? • Design abstraction: HDL ↔ layout by human • Hardware modeling • Reduce cost and time to design hardware • Verilog is one of the most popular HDLs • VHDL (another popular HDL) • Key features of Verilog • Supports various levels of abstraction • Behavior level • Register transfer level • Gate level • Simulate design functions • Combines structural and behavioral modeling styles ESA Laboratory

5. System Specification Suitable for all levels Behavioral level Not suitable HW/SW Partition Hardware Spec Softwre Spec ASIC Boards & Systems FPGA Software PLD Std Parts Application Areas of Verilog ESA Laboratory

6. Hardware Design Flow Designer Level Cost High Low RTL Simulation RTL Editor Verilog RTL Code Gate Level Simulation Logic Synthesis Gate Level Code Post Gate Level Simulation Place & Route Physical Layout Tape Out Low High Chip ESA Laboratory

7. Verilog Modeling • When Verilog was first developed (1984) • Most logic simulators operated on netlists • Netlist: list of gates and how they’re connected • Structural modeling • A natural representation of a digital logic circuit • Not the most convenient way to express test benches • Behavioral modeling • A much easier way to write testbenches • Also good for more abstract models of circuits • Easier to write, Simulates faster • More flexible • Provides sequencing • Verilog allows both the model and the testbench to be described together ESA Laboratory

8. Verilog Language • Describe a system by a set of modules • Equivalent to functions in ‘C’ • Keywords • E.g., module, are reservedin all lower case letter • Operators (some examples) • Arithmetic: +, -, *, /, !, ~ • Binary operators: &, |, ^, ~, ! • Shift: <<, >> • Relational: <, <=, >, >=, ==, != • Logical: &&, || • Identifiers • Equivalent to variable names • Identifiers can be up to 1024 characters • Comments • “//” for 1-line or /* to */ across several lines ESA Laboratory

9. Four Valued Data • Verilog’s nets and registers hold four-valued data • 0, 1 • Obvious • Z • Output of an undriven tri-state driver • Models case where nothing is setting a wire’s value • X • Models when the simulator can’t decide the value • Initial state of registers • When a wire is being driven to 0 and 1 simultaneously • Output of a gate with Z inputs ESA Laboratory

10. Number Representation • <size><base format><number> • <size>: Number of bits (optional) • <base format>: Single character (b, d, o, and h) • <number>: Contains digits which are legal for the <base format> • Examples • 549 // decimal number • ‘h8FF // hex number • ‘o765 // octal number • 4’b11 // 4-bit binary number 0011 • 3’b10x // 3-bit binary number with least significant bit unknown • 5’d3 // 5-bit decimal number • -4’b11 // 4-bit two’s complement of 0011, or equivalently 1101 ESA Laboratory

11. Two Main Components of Verilog • Concurrent, event-triggered processes (behavioral) • Initial and Always blocks • Imperative code that can perform standard data manipulation tasks (assignment, if-then, case) • Processes run until they delay for a period of time or wait for a triggering event • Structure (Plumbing) • Verilog program build from modules with I/O interfaces • Modules may contain instances of other modules • Modules contain local signals, etc. • Module configuration is static and all run concurrently ESA Laboratory

12. Two Main Data Types • Nets(wire) represent connections between things • Do not hold their value • Take their value from a driver such as a gate or other module • Cannot be assigned in an initial or always block • Regs(reg) represent data storage • Behave exactly like memory in a computer • Hold their value until explicitly assigned in an initial or always block • Never connected to something • Can be used to model latches, flip-flops, etc. • Shared variables with all their attendant problems • A variable of type register does not necessary represent a physical register ESA Laboratory

13. Size in the Declaration • Size of register or wire reg [0:7] A, B; // A and B are 8-bit wide with MSB as 0th bit wire [3:0] Dout; // Dout is a 4-bit wire reg [7:0] C; // C is 8-bit register with MSB as the 8th bit • Assignments and concatenations • A = 8’b0101_1010; • B = {A[3:0] | A[7:4], 4’b0000}; • B is set to the 1st 4-bit of A bitwise or-ed with the last 4-bit of A and then concatenated with 0000. • {} brackets means the bits of the 2 or more arguments separated by commas are concatenated together. ESA Laboratory

14. Module • Represents bits of hardware ranging from simple gates to complete systems, e.g., ‘ARM9’ • The structure of a module is the following: module <module name> (<port list>); <declaration> <module items> endmodule ESA Laboratory

15. ExampleⅠ: 1-bit Multiplexer ESA Laboratory

16. Behavioral Level / RTL Description always block assign • Variable names • All undeclared variables are wires and are one bit wide. • Good Practice • : Declare all variables!! ESA Laboratory

17. Gate Level Description • Gate Level • You see only netlist (gates and wires) in the code ESA Laboratory

18. A S B C A S half_ adder B C ExampleⅡ: Half Adder for Full Adder • Half adder ESA Laboratory

19. in1 I1 sum I2 I3 in2 cout A S half_adder ha1 cin B C A S half_adder ha2 B C ExampleⅡ: Full Adder • Full adder • ‘half_adder’ instances are connected to make ‘full_adder’ ESA Laboratory

20. ‘always’ Blocks • Start execution at sim time zero and continue until sim finishes always @(…) begin …… end • @ • Execution triggers every time any signal changes always @(sig1 or sig2 or sig3 or..) begin …… end • Execution triggers every time clock changes from 0 to 1 always @(posedge clock) begin …… end • Execution triggers every time clock changes from 1 to 0 always @(negedge clock) begin …… end ESA Laboratory

21. reset_n a Y b c W clock Example: ‘always’ ESA Laboratory

22. Procedural Statement: if • Usage if (expr1) true_stmt1; else if (expr2) true_stmt2; .. else default_stmt; ESA Laboratory

23. Procedural Statement: case • Usage case (expr) item_1,… , item_n : stmt1; item_n+1, …, item_m: stmt2; .. default: default_stmt; endcase ESA Laboratory

24. Blocking / Non-blocking assignment • Blocking assignment (= operator) • Acts much like in traditional programming languages • The whole statement is done before control passes on to the next statement. • Non-blocking assignment (<= operator) • Evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit • Let’s think the meaning of ‘non-blocking’ • Real H/W registers should be assigned with non-blocking • Example ESA Laboratory

25. Finite State Machines • FSM consists of: • A set of input events (input signals, including clock) • A set of output events (output signals) • A set of states (state variables are FFs) • A function that maps states and input to output (output logic) • A function that maps states and inputs to states (next-state logic) • A description of the initial state (initial FF value) • FSM is one that has a limited, or finite, number of states. • The machine state is described by a collection of state variables. • FSM is an abstract concept, and may be implemented a variety of techniques, including digital logic. ESA Laboratory

26. ExampleⅠ: Simple FSM • Simple FSM which has 3-states • Suppose there are three desired outputs: • odd • even • terminal restart or pause terminal=0 FIRST even=0 odd=1 !restart and !pause terminal=0 restart or !pause terminal=1 restart terminal=0 SECOND even=1 odd=0 THIRD even=0 odd=1 !restart and !pause terminal=0 !restart and pause terminal=0 !restart and pause terminal=0 ESA Laboratory

27. ExampleⅠ: Simple FSM • Output signals • ‘odd’ : asserted in FIRST and THIRD state • ‘even’: asserted in SECOND state • ‘terminal’: asserted to indicate the FSM will transition from THIRD to FIRT • Moore type outputs • Require functions of only the current state • This includes using state bits directly. • Outputs ‘odd’ and ‘even’ are Moore outputs. • Mealy type outputs • Require functions of the current state and the inputs • Output ‘terminal’ is a Mealy output. • Consider the latency and cycle time tradeoffs. ESA Laboratory

28. ExampleⅠ: Simple FSM • Block diagram • This FSM can be simplified as shown in below block diagram. ESA Laboratory

29. ExampleⅠ: Simple FSM • Verilog code restart or pause terminal=0 FIRST even=0 odd=1 !restart and !pause terminal=0 restart or !pause terminal=1 restart terminal=0 SECOND even=1 odd=0 THIRD even=0 odd=1 !restart and !pause terminal=0 !restart and pause terminal=0 !restart and pause terminal=0 ESA Laboratory

30. ExampleⅠ: Simple FSM • Signal waveform clk state[1:0] FIRST SECOND THIRD FIRST SECOND FIRST SECOND THIRD FIRST SECOND THIRD next_state [1:0] SECOND THIRD FIRST SECOND FIRST SECOND THIRD FIRST SECOND THIRD FIRST restart pause ESA Laboratory

31. NC-Verilog Simulation

32. Testbench • Test methodology • Systematically verify the functionality of a model. • Simulation • Detect syntax violation in source code • Simulate behavior • Monitor results ESA Laboratory

33. Testbench Example: 4-to-1 Mux Inputs to device under test Device under test $monitor is built-in driven ‘$printf’ ESA Laboratory

34. Verilog Simulator ESA Laboratory

35. Simulation with NC-Verilog • What is NC-Verilog? • One of the most popular verilog simulator developed by Cadence. • VCS(Synopsys), ModelSim(Mentor Graphics), etc… • Native Compiled code • Software execution technique that provides a high-performance solution to the simulation performance bottleneck • Interleaved Native Compiled Code Architecture (INCA) • Multiple language / levels / paradigms, Mixed signal • IUS package • IUS: Incisive Unified Simulator • Support simulator commands for • Compile • Elaboration • Simulation • Simvision tool for waveform debugging ESA Laboratory

36. NC-Verilog Simulator ESA Laboratory

37. NC-Verilog Simulator • Simulation by running the following tools: • ncvlog • Compiles the Verilog source files • ncelab • Elaborates the design and generates a simulation snapshot • ncsim • Simulates the snapshot • Above tools can be run in single-step invocation mode with the ‘ncverilog’ command • `timescale compiler directive is needed. • Ex: `timescale 1ns/10ps ESA Laboratory

38. Simple Simulation command • FSM simulation procedure • Prepare verilog files • fsm.v, tb_fsm.v • These file names can be listed in ‘file_list.f’ with file path. • Command • ncverilog +access+rwc \ -f ./file_list.f \ +licq_vxl +define+functional_mode+no_mem_message \ -l ./LOG/tb_fsm.log \ +loadpli1=debpli:debPLIPtr • Signal dump option initial begin $shm_open(“$SIM_PATH/tb_fsm.shm”, 1); $shm_probe(tb_fsm); end ESA Laboratory

39. Debugging with Signal Viewer ESA Laboratory

40. Design Synthesis

41. Logic Synthesis with Design Compiler • Design Compiler (DC) • The core of the Synopsys synthesis software products • Include tools that synthesis the HDL designs into optimized technology-dependent, gate level designs • Optimize for speed, area and power. • Basic synthesis flow Mapped technology dependent netlists (Go for P&R, Post layout synthesis) DESIGN COMPILER Verilog Files Synthesis; Optimize for speed & area & power ESA Laboratory

42. Synthesis, Optimization and Compilation • Synthesis • Process to generate a gate-level netlist for an IC design that has been defined using a Hardware Description Language (HDL). • Synthesis includes reading the HDL source code an optimizing the design from that description. • Optimization • The step in the synthesis process that attempts to implement a combination of library cells that best meet the functional timing, and area requirements of the design. • Compilation • DC command and process that executes the optimization step • After reading in the design performing the necessary tasks, the compile command is invoked to generate a gate-level netlist for the design. ESA Laboratory

43. Synthesis Flow (1) • Specifying libraries • Link and target libraries • Define the semiconductor vendor's set for cells and related information, such as cell names, cell pin names, delay arcs, pin loading, design rules and operating conditions • Symbol library • Define symbols for schematic and viewing the design • Reading, Analyzing and Elaborating designs • Read • Loading into the memory (to see the designs loaded, use list_designs) • Analyze • Reading HDL source file / Checking errors • Create HDL library objects in an HDL intermediate format • Elaborate • Create a technology-independent design from the intermediate files ESA Laboratory

44. Synthesis Flow (2) • Defining the design environment • Operating condition • Temperature, voltage, and process variations • Wire load models estimate the effect of wire length on design performance • Wire load modeling allows designer to estimate the effect of wire length and fanout on the resistance, capacitance, and area of the nest • System interface characteristics • Include input drives, in/out loads and fan-out loads • The environment model directly affects the design synthesis result • Example • set_operating_conditionsWC: for setting the operating conditions to the worst case • set_wire_load "10x10" ESA Laboratory

45. Synthesis Flow (3) • Setting the design constraints • Design rule constraints • Implicit design rules specified in the technology library • Stricter design rules specified by user • Examples:Set_max_fanout16Set_max_capacitance3 • Optimization constraints • Define timing and area optimization goals for Design Compiler. • These constraints are user-specified. • Examples:create_clock clk1 –period 40max_area 100 ESA Laboratory

46. Synthesis Flow (4) • Setting the design constraints • Optimization constraints – Cont’d • Examples: ESA Laboratory

47. Synthesis Flow (5) • Design optimization • Synthesis step that maps the design to an optimal combination of specific target library cells, based on the design’s functional, speed and area requirements • Architectural optimizing • Structuring • Adds intermediate variables and logic structures to a design, which can result in reduced design area- set_structure-flag true -boolean_effort 3 –deisgndeaignName • Flattening • Useful for speed optimization because it leads to just two levels of combinational logic • It is preferred to do Flattening for logic in the critical path only for huge designs- set_flatten -flag true -effort 3 –deisgndeaignName ESA Laboratory

48. Synthesis Flow (6) • Gate level optimizing • Area optimization • The process goal is to meet the area constraints after the previous three steps. • Command: compile area_effort high • Performing high-effort incremental compile • May improve the compile performance of a high effort compile • It experiments deferent approaches for gate level optimization • Command: compile –map_effort high –incremental_mapping ESA Laboratory

49. Synthesis Flow (7) • Analyze and resolve the design problem • Commands: • check_design • report_area • report_constraint • report_timing ESA Laboratory

50. DC Script Example ESA Laboratory