D Flip Flop

1. D Flip Flop

2. Also called: • Delay FF • Data FF • D-type Latches • ‘Delayed 1 • Clock Pulse’

3. D Flip Flop (Specification) • A signal input and a clock signal is used • AMI-0.6micron process is used • Wp=7.5 u, Wn= 3.0 u, Ln=Lp=0.6u • Pre and Post-layout simulations using spectra • Rise time, Fall time and propagation delay increase for the loading effects.

4. Why DFF • Preferred type for integrated circuit applications (DFF) • S-R flip flop has indeterminate state when both inputs are high • The JKFF simplifies the RSFF truth table but keeps two inputs.

5. Symbol

6. Truth Table Similar Wiring

7. Wiring Diagram

8. 7474 D Flip Flop • Logic Symbol Note: The asynchronous inputs (PS & CLR) Override the synchronous inputs (D & CLK) .

9. Truth Table

10. D (Delay) Flip Flop Uses • Sequential logic devices used in temporary memory devices. • Wired together to form shift registers and storage registers. • Delays data from reaching output Q one clock pulse. • CMOS examples: 74HC74, 74FCT374, 40174 • Over 50 different ICs in FACT CMOS family.

11. D Clocked Latch It similar to a D flip flop but it reacts to the clock differently

12. Comparing Flip Flop and Latch

13. D Flip Flop vs. D Clocked Latch • D flip flop • Triggered on positive edge of clock • Output Q (and state) changes only at a time instant • D clocked latch • Output Q changes (with D) while clock is H • Output Q changes during a window of time • Trickier to use since lots of changes can happen during a time duration • Flip flops are preferred to latches in designing circuits • Latches are used in memory circuits, e.g., RAM

14. The End Thank you