Advanced Digital Design

1. Reconfigurable Logic Advanced Digital Design by A. Steininger and M. DelvaiVienna University of Technology

2. Outline • Introduction • Reconfigurable Logic Issues • Conclusion • Research plans

3. … in the `40s Problem: How can we use the same hardware platform for different applications ? Answer: Microcontroller concept: Map each application to the same instruction set This is an extremly flexible, but also an ineffiecient approach

4. A New Paradigm Reconfigurable hardware allows to tailor the same hardware to individual applications „on the fly“: • Techniques used for software development can be applied to hardware • Problem specific circuits allows highly efficient computations Key technology  FPGA

5. FPGA (1) LE LE LE programmable switch matrix LE LE LE • Programmable logic elements • Programmable interconnects

6. FPGA (2) LE LE LE Inputs Outputs LE LE LE Resulting circuit Configuration memory • Configuration memory is SRAM based: • „fast“ reconfiguration • multiple reconfigurations possible ( > 100.000)

7. Reconfigurable Logic Issues When What Who Why

8. Reconfigurable Logic Issues What Who Why When

9. Reconfigurable Logic Issues When does the reconfiguration take place ? • Once (at start-up) • During operation • Offline reconfiguration • operation stops • new configuration is loaded • operation continues • Run-time reconfiguration  reconfiguration is performed during normal operation

10. Reconfigurable Logic Issues When Who Why What

11. What is reconfigured 1) Entire FPGA cfg data Configuration memory Configuration memory LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE 2) Parts of the FPGA LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE cfg data Configuration memory Configuration memory 3) Multi-context reconfiguration cfg data Configuration memory Configuration memory

12. Reconfigurable Logic Issues When What Why Who

13. Who reconfigures • One central controller • External New configuration can be „downloaded“ from outside • Internal Internal controller calculates and executes the configuration • Distributed „controller“ • Intelligent Each part of the system can decide on the need for rearrangement. • Unintelligent Reconfiguration takes place according predifined rule in response to external events

14. Reconfigurable Logic Issues When What Who Why

15. Why Reconfiguration • Rapid Prototyping

16. Rapid Prototyping (1) • First transistor (1947) • Discrete devices (Mailüfterl,1958) • TTL circuits -> 7400 Series (197x) • Programmable Logic Devices (PLD) • PLA, PAL, CPLD => Antifuse, (E)EPROM • Gate Arrays -> customization only in the last fabrication step • Field Programmable Gate Arrays (FPGAs)

17. Rapid Prototyping (2) Advantage of FPGA: • Short design cycles • Reduce costs • Design space exploration • Valuable prototypes • Suitable for small number of pieces • Hardcopy • …

18. Why Reconfiguration • Rapid Prototyping • Save Logic Elements

19. Save Logic Elements (1) • Time sharing: Programmable logic can be used to implement different modules in a device • Example: Mobile phone • Virtualization: Programmable logic is used to „provide“ an infinite amount of logic • Compare: Physical and virtual memory

20. Virtual Hardware: The PipeRench Example (1) Virtual Circuit Mapping: 5 → 3 Pipestages PhysicalCircuit Stage2 Stage3 Stage1 Principle: 5 2 3 1 4 ? ? ? cfg4 exe4 exe4 cfg2 cfg5 exe5 exe5 exe2 exe3 exe3 cfg1 exe1 … configuration … execution cfg exe cfg1 exe1 exe1 exe2 cfg2 cfg3

21. Virtual Hardware: The PipeRench Example(2) Advantages: • Implementation of large virtual circuit in small physical devices • Scalable performance Limitations: • Cycle dependency must fit in one pipeline stage • Configuration must be performed in one clock cycle

22. Why Reconfiguration • Rapid Prototyping • Save Logic Elements • Improve Performance

23. Improve Performance C-CoP • Application specifics circuits • Data driven computation • Partial reconfiguration 1) (Soft)-CPU + Configurable Instructions 2) (Soft)-CPU + Configurable CoProcessor (Soft)-CPU CI • Hardware Contex Switch

24. Hardware Context Switch Context switching Task A.1 CSW Task A.2 CSW Task A.3 LE LE LE Inputs Outputs LE LE LE Configuration Memory Several configurations in the config memory Configuration Memory Configuration Memory Static Task A time

25. Why Reconfiguration • Rapid prototyping • Save logic elements • Improve performance • Increase fault tolerance / self healing circuits

26. Increase fault tolerance (1) • Spare programmable logic replace faulty compoments • Requirements • Error detection • Diagnosis • Replacement strategy • Recovery • Parameters: • Block size • Detection delay • Recovery time • Overhead

27. Increase fault tolerance (2) Function D Function D Function A Function A Function B Function C Function C Function B Unused Unused Col1 Col1 Col2 Col3 Col4 Col5 Col5 Col2 Col4 Col3 • Examples: • FPGA based TMR • Column based precompiled configuration technique Limited changes  simple rerouting

28. Increase fault tolerance (3) k k LUT k k LUT k k LUT k Fault Flag LUT XOR k k Outputs LUT k k LUT k k LUT • Example: • FPGA based TMR • Coloum based precompiled configuration technique • Fine-grained self healing hardware Inputs

29. Global Challenges in Reconfigurable Computing • Time required for reconfiguration • Overhead for reconfigurability • Block size • Configuration data: • Precompiled modules -> memory overhead • Run time generated modules–> additional (intelligent) controller • Software tools

30. Conclusion • Reconfigurablelogic changes the traditional way to implement digital systems: • Hardware is becoming flexible as software • Arbitrarily combination of methodes presented in section „When, What, Who, Why“ • …

31. Our Research Activities • Asynchronous logic • Optimization wrt: • Power Consumption • Area Overhead • Performance • Reconfigurable logic • Fault Tolerance / Self healing circuits • Combination of both research domains