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Asynchronous Design: FSL. Advanced Digital Design. by A. Steininger and M. Delvai Vienna University of Technology. Outline. Introduction Principles Basic gates Design flow and tools Circuit design with FSL Pipeline Data paths Current status Conclusion. Fundamental Design Problem.
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Asynchronous Design: FSL Advanced Digital Design by A. Steininger and M. DelvaiVienna University of Technology
Outline • Introduction • Principles • Basic gates • Design flow and tools • Circuit design with FSL • Pipeline • Data paths • Current status • Conclusion
Fundamental Design Problem f(x) SRC SNK Issue Condition Capture Condition Ensure a lossles data flow new data can be issued, when the previous one was already consumed only valid and consistent data has to be consumed A
Synchronous Approach TClk f(x) SRC SNK Global Time Reference => indirect conclusion A
Asynchronous Circuits Request f(x) SRC SNK Acknowledge local handshake protocol
Four State Logic => delay insensitive 1x „1“ | 2x „0“ 2x „1“ | 1x „0“ 3x „1“ | 2x „0“ f(x) SRC SNK ∆t => SNK must able to recognize when data is valid and consistent => additional information required
FSL encoding Use 2 codes per logic value need two-rail coding: X.a X X.b (1,0) (0,0) ? (1,1) = L = l (0,1) = h = H (0,0) => (1,1) L => H
Completion Detection H l L h H h L l consistent data SRC SNK
FSL Gates • Combinational Gates • AND, OR, INV, …
Phase Transition ? f(x) φ0 φ1 φ0 φ1 • We have to ensure, that: • unconsistent input vectors are not processed • f(x) is a monotonic function
Combinational Functions • Consistency detector C D Processing of unconsistent inputs inevitable due to internal skew local intelligence => hardware overhead Variant 1: Variant 2: • each basic gate processes only const. inputs f(x) • Hazard free impl. • function of each basic gate is monotonic
Combinational Gates And Or Inv (MUX) (XOR) … Truth Table FSL-AND E2 Consistent in φ1 E1 Y l h L H FSL AND Y * * l E2 * * h E1 * * L * * H Consistent in φ0 l l l h L L L H * keep old value
Gate Template E1.a E1 fa(x) Mem Y.a E1.b Y Y.b E2.a E2 fb(x) Mem E2.b Challenge: preserve the delay insensitive for implementation
0 (a,b) 1 (a,b) LOW L (0,1) l (0,0) H (1,0) HIGH h (1,1) rail a rail b Inverter Is the inverter delay insensitive?
FSL Gates • Combinational Gates • AND, OR, INV, … • Register
Completion Detection H l L h H h L l consistent data SRC SNK
Completion Detection H l L h H h L l consistent data SRC SNK Latch CMPD enable Register
FSL Register Latch Latch CMPD CMPD CMPD L A T C H L A T C H L A T C H L A T C H f(x) f(x) f(x) additional handshake signals are required
FSL Register CTRL CMPD L A T C H L A T C H L A T C H L A T C H f(x) f(x) f(x) input data output data Latch CMPD Is the output data already consumed ? handshake signal from the next register required
FSL Register CMPD input data output data Latch CTRL CMPD When do we close the latch again ? when the input data was taken over
FSL Register Input data is ready to be consumed when all input signals carry the same phase Input data is consumed when input and output carry the same phase CMPD Output data was consumed when the output of the next register carry the same phase as the current output data input data output data Latch CTRL CMPD => phase detector => phase detector => phase detector Only phase detectors are required to generate all handshake signals
φ–Detector XOR XOR ‘0‘ ‘1‘ 0 (a,b) 1 (a,b) LOW l (0,1) L (0,0) h (1,0) HIGH H (1,1)
Latch Latch Latch Latch φ φ out in pass FSL Register • input data consistent and valid • output data already consumed data out data in • freeze the latches again • input data input data consumed Ctrl c-done
FSL Gates • Combinational Gates • AND, OR, INV, … • Register • Latch • φ–Detector • Memory
Memory Two options: • Store directly FSL signals • 4 bits per logical value • huge overhead but delay insensitive (in theory) • Store only logical information • 1 bits per logical value • low overhead but not delay insensitive
Memory FSL_Logic STD_Logic FSL_Logic STD_Logic C O N V Standard RAM C O N V φ-det
φ–Converter Std → FSL FSL → Std Std rail a FSL rail a FSL Std X O R rail b rail b requested φ Std logic FSL logic 0 (a,b) 1 (a,b) Sig. LOW LOW 0 L (0,0) l (0,1) H (1,1) h (1,0) HIGH 1 HIGH
FSL Gates • Combinational Gates • AND, OR, INV, … • Register • Latch • φ–Detector • Memory • φ–Converter (FSL→Std, Std→FSL) • φ–Inverter
0 (a,b) 1 (a,b) LOW L (0,1) l (0,0) H (1,0) HIGH h (1,1) rail a rail b φ–Inverter => simple inversion of rail b
FSL Gates • Combinational Gates • AND, OR, INV, … • Register • Latch • φ–Detector • Memory • φ–Converter (FSL→Std, Std→FSL) • φ–Inverter
Design Flow and tools Requirements: • Standard tools (Synopsys/Quartus) • Modelling on RTL level • Support for simulation and synthesis • Target platform FPGA
Adaptation: VHDL • Definition of an FSL_logic type • Redefinintion of std_1164 package • Additional functions • φ_det, φ_inv, conversion functions • stable => Modelling FSL circuits on RTL level
Example: Program Counter JmpExe JmpAddr f(x) AddrNxt AddrInc stable_signals <= AddrInc&JmpExe&JmpAddr; pc_next: process begin stable(stable_signals); if JmpExe = ‘H‘ or JmpExe = ‘l‘ then AddrNxt <= JmpAddr; else AddrNxt <= AddrInc; end if; end process pc_next;
Adaptation: Synthesis (1) L L & H (0,0) (0,0) & (1,1) • FSL Target FSL Library • FSL AND, FSL OR , FSL INV, FSL Register, φ-Detector … • Synthesis with FSL Target Library • Netlist • Package FSL_Rail • Definition FSL_rail_logic :Record (a,b) • FSL AND, FSL OR , FSL INV, FSL Register, φ-Detector … • Netlist: Replace FSL with FSL_rail • Synthesis with FPGA Target Library
Adapation: Synthesis (2) conventional design flow FSL design flow
Adaptation: Simulation FSL Stimuli FSL Response Conversion Conversion FSL Logic FSL Rail Logic Testbench • Same testbench for FSL_logic and FSL_rail_logic ciruits => Verification of FSL circuits
Outline • Introduction • Principles • Basic gates • Design flow and tools • Circuit design • Pipeline • Data Paths • Current status • Conclusion
(Linear) Pipeline L A T C H L A T C H L A T C H L A T C H f(x) f(x) f(x) 0 0 0 1 0 0 1 0 0 0 K2 K3 K4 K1 Empty initialized Full initialized
Bubble Concept (1) 0 1 0 1 0 K2 K3 K4 K1 bubble identical values 0 1 0 1 1 K2 K3 K4 K1 Progress is possible when a circuit contains at least one bubble
Bubble Concept (2) 1 1 1 1 0 0 0 0 K2 K3 K4 K5 K6 K7 K1 • Initialization => ensure that the circuit contains at least one bubble • More than one bubble => higher processing speed
Bubble Concept (3) SRC SNK • Bubbles can be consumed: • Slow SRC → empty pipeline • Slow SNK → full pipeline 0 1 1 1 1 0 K2 K3 K4 K5 K6 bubble
Non-linear Pipeline feedback path K2 K3 K4 K5 K6 K1 forward path Definition: A non-linear pipeline is a pipeline which contains at least one feedback or forward path • Consequences: • Internal regulation bubble cannot be consumed • Potential sources of deadlocks
Non-linear Pipeline: Forward Path (1) φ-inv SNK SRC 0 1 0 1 0 1 0 K2 K3 K4 K1 1 request
Non-linear Pipeline: Forward Path (2) 4 3 2 1 0 1 0 1 φ-inv 0 1 Operation 0 K2 K3 K4 K1 0 1 0 1 1 0
Non-linear Pipeline: Forward Path (2) 5 0 φ-inv Operation 0 1 0 1 1 K2 K3 K4 K1 1 0
Empty Non-linear Pipeline: Forward Path (1) 0 1 0 1 0 0 0 0 0 0 1 0 0 K2 K3 K4 K1 φ-inv 1 empty initialized => no phase inverter is required
Empty Non-linear Pipeline: Forward Path (2) 4 3 2 1 φ1 1 φ1 1 Operation 0 K2 K3 K4 K1 0 0 0 0 φ1 0 => different phase inverter placement for full and empty initialized circuit
Conclusion:Feedforward Paths switching sequence switching sequence K2 K3 K4 K2 K3 K4 K1 K1 0 1 0 1 0 0 0 0 0 0 φ-inv 0 1 0 Empty initialized Full initialized • Ensure consistent inputs • Phase inverter placement depends on initialisation
Non-linear Pipeline: Feedback Path (1) φ-inv 0 1 Operation 0 K2 K3 K4 K1 0 1 0 1
Non-linear Pipeline: Feedback Path (2) 3 2 1 1 0 1 φ-inv 0 1 Operation 0 K2 K3 K4 K1 0 1 0 1 0 1
