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Chapter 6 (I)

Chapter 6 (I). Designing Combinational Logic Circuits Static CMOS Pass Transistor Logic. V1.0 4/25/2003 V1.1 5/2/2003 V2.0 5/4/2003. Revision Chronicle. 5/2: Add some NAND8 figures (to compare NAND8 circuits) from old Weste textbook to this slide. 5/4:

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Chapter 6 (I)

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  1. Chapter 6 (I) • Designing CombinationalLogic Circuits • Static CMOS • Pass Transistor Logic V1.0 4/25/2003 V1.1 5/2/2003 V2.0 5/4/2003

  2. Revision Chronicle • 5/2: Add some NAND8 figures (to compare NAND8 circuits) from old Weste textbook to this slide. • 5/4: • Add 4 Pass-Transistor Logic Slides from Weste textbook • Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic

  3. Combinational vs. Sequential Logic Combinational Sequential Output = ( ) f In, Previous In Output = ( ) f In

  4. V or V DD ss Static CMOS Circuits • At every point in time (except during the switching transients) each gate output is connected to either • via a low-resistive path (PUN, PDN) • The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring the transient effects duringswitching periods). • This is in contrast to the dynamic CMOS circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

  5. VDD In1 PMOS only (good for transfer 1) In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only (good for transfer 0) InN Static Complementary CMOS Pull-up Network (PUN) and Pull-down Network (PDN) are Dual Logic Networks

  6. CL CL CL CL Threshold Drops in NMOS and PMOS-- Check Candidates for PUN and PDN VDD VDD PUN S D G VDD G D S 0 VDD 0 VDD - VTn VGS PDN VDD 0 VDD |VTp| VGS D S VDD G G S D

  7. Complementary CMOS Logic Style

  8. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

  9. PMOS Transistors in Series/Parallel Connection

  10. Example 1: NAND2 Gate (Use DeMorgan’s Law)

  11. Example2: NOR2 Gate

  12. B A C D Design of Complex CMOS Gate A D B C

  13. Constructing a Complex Gate SN2 SN1 SN2 SN1

  14. Static CMOS Properties • Full rail-to-rail swing: High noise margins • Logic levels not dependent upon the relative device sizes: Ratioless • Always a path to Vdd or GND in steady state: Low output impedance • Extremely high input resistance; nearly zero steady-state input current (input to CMOS gate) • No steady-state direct path between power and ground: No static power dissipation • Propagation delay function of output load capacitance and resistance of transistors

  15. Rp Rp Rp Rp Rp Rp A A A B B A Cint Rn CL CL CL Rn Rn Rn Rn B A B A A Cint Switch Delay Model Req A A NOR2 INV NAND2

  16. Rp Rp B A Cint CL Input Pattern Effects on Delay • Delay is dependent on the patternof input (Assume Rp = 2 Rn for same size of transistors) • Low-to-high transition: • Both inputs go low • Delay is 0.69 (Rp/2) CL • One input goes low • Delay is 0.69 (Rp) CL • High-to-low transition: • Both inputs go high (required for NAND) • Delay is 0.69 (2Rn)CL Rn B Rn A

  17. Rp Rp 2 2 Rp Rp B A A B Cint Cint CL CL Rn Rn Rn A B B 1 1 Transistor Sizing Assumes Rp = 2Rn at same W/L 4 4 Rn 2 2 A NAND is preferred than NOR implementation!!

  18. Delay Dependence on Input Patterns NAND2 is true OUT connects to GND A=B=10 A=10, B=1 Voltage [V] A=1, B=10 time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF A=1, B=10 (for both Cint and CL) A=1, B=01 (Consider Body effect)

  19. A D Transistor Sizing a Complex CMOS Gate B 8 4 C 8 4 OUT = D + A • (B + C) A 2 D 1 B 2 C 2

  20. Fan-In Considerations 4-input NAND Gate

  21. A B D C B A C1 C3 C2 CL C D Fan-In Considerations Distributed RC model (Elmore delay) tpHL = 0.69(R1C1+(R1+R2)C2 + (R1+R2+R3)C3 + (R1+R2+R3+R4)CL =0.69 Reqn(C1+2C2+3C3+4CL) R4 R3 R2 R1 Propagation (H L) delay deteriorates rapidly as a function of fan-in no. : Quadratically in the worst case.

  22. Quadratic (H->L) tpHL tp tp as a Function of Fan-In tp (psec) tpLH (L  H) Linear Increase in Intrinsic Capacitance, Assume Only one PMOS is On for critical case fan-in

  23. (tpHL, tpLH) as a Function of Fan-Out Gates with a fan-in greater than or equal to 4 becomes excessively slow and should be avoided!

  24. tp as a Function of Fan-In and Fan-Out • Fan-in: quadratic due to increasing resistance and capacitance • Fan-out: each additional fan-out gate adds two gate capacitances to CLTo the preceding stage)

  25. C3 C2 C1 CL Fast Complex Gates: Design Technique 1 • Transistor sizing • Increase Intrinsic parasitic cap and create CL of the preceding stage • Progressive sizing • Distributed RC line: • M1 > M2 > M3 > … > MN • (the FET closest to the • output is the smallest) • Not simple in Layout! InN MN In3 M3 In2 M2 In1 M1

  26. Fast Complex Gates: Design Technique 1

  27. C2 C1 C1 C2 CL CL Fast Complex Gates: Design Technique 2 • Input reordering: Put late arrival signal near the output node. critical path critical path 01 charged charged 1 In1 In3 M3 M3 1 1 In2 In2 M2 discharged M2 charged 1 In3 discharged In1 charged M1 M1 01 Delay determined by time to discharge CL, C1 and C2 Delay determined by time to discharge CL

  28. Fast Complex Gates: Design Technique 3 • Logic Restructuring (A) F =NAND8 Gate (C) (B) In general,C > B > A in speed

  29. Design Technique 3: Logic Restructuring Tradeoff between Area and Speed (and Power?) (from Neil Weste, 2nd Ed, 93)

  30. CL CL Fast Complex Gates: Design Technique 4 • Isolating fan-in from fan-out using buffer insertion

  31. Fast Complex Gates: Layout Technique (A): 4 internal cap 2 output diff cap (B): 4 internal cap 4 output diff cap (A) Is better than (B) (A) (B)

  32. Out In CL N 2 1 Optimizing Performance in Combinational Networks (in units of tinv) For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any combinational logic path? E.g., How do we size the ALU datapath to achieve maximum speed?

  33. Logical Effort • Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates • Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current • Logical effort increases with the gate complexity

  34. Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 5/3 g = 4/3 g = 1

  35. Logical Effort From Sutherland, Sproull

  36. Estimated Intrinsic Delay Factor

  37. Logical Effort p – intrinsic delay : gate parameter g – logical effort : gate parameter f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1.

  38. Delay in a Logic Gates Gate delay: d = h + p Effort delay Intrinsic delay Effort delay: h = g f Logical Effort Effective fanout =Cout/Cin • Logical effort is a function of topology, independent of sizing • Effective fanout (electrical effort) is a function of load/gate size

  39. Logical Effort of Gates

  40. Logical Effort of Gates t pNAND g = 4/3 p = 2 d = (4/3)f+2 t pINV Normalized delay (d) g = 1 p = 1 d = f+1 F(Fan-in) 1 2 3 4 5 6 7 Fan-out (f)

  41. Add Branching Effort Branching effort:

  42. Multistage Networks • Stage effort: hi = gifi • Path electrical effort: F = Cout/Cin • Path logical effort: G = g1g2…gN • Branching effort: B = b1b2…bN • Path effort: H = GFB • Path delay D = Sdi = Spi + Shi

  43. Optimum Effort per Stage When each stage bears the same effort: Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: Minimum path delay

  44. Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’

  45. Example: Optimize Path g = 1f = a g = 1f = 5/c g = 5/3f = c/b g = 5/3f = b/a Effective fanout, F = 5 G = 25/9 H = GF=125/9 = 13.9 h = 1.93 (optimal stage effort) = a = 1.93 b = ha/g2 = 2.23 c = hb/g3 = 5g4/f = 2.59

  46. Example – 8-input AND

  47. Method of Logical Effort • Compute the path effort: F = GBH • Find the best number of stages N ~ log4F • Compute the stage effort f = F1/N • Sketch the path with this number of stages • Work either from either end, find sizes: Cin = Cout*g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

  48. Summary Sutherland, Sproull Harris

  49. Pass-TransistorLogic

  50. Pass-Transistor Logic

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