Pulsed Power System Issues

1. Pulsed Power System Issues Peter Göttlicher, DESY-FEB TWEPP 2012 Oxford , September 19th, 2012

2. Where to look at: Building Blocks for the Power System DAQ is Optical: No issue for EMI Planes with current-pulsed consumersin very limited space and no cooling. sensors, ASICS, PCB’s 4. Power supply 3. Cable and their supports Frequencies: Train-rate: 5 / 50Hz to ASIC rise/fall: >100MHz, SPIROC Needed, optimal? Lengths of train 1ms/0.2µs Risk to interfere with others 2. End of layer electronics Cooling, more space, not plenty Increasing frequency, increasing loneliness, decreasing risk to interfere

3. Technique in the active layer: Closing current loops near ASIC Simulation: - Capacitors mounted to the 36x36cm2 PCB - Power-GND layers at 50µm distance (60pF/cm2) Simulation of voltage induced by current ASIC is supported Z< 0.1W for wide range Oscillations are dumped - phase ¹ ±900 for wide range Þgood, it dumps oscillation - Its simulated without possible resistive behavior of ASIC. C-R-combination reduces phase jumps. Result: - Locally good for > 10kHz - Additional effort < 10kHz ÞIn the end-of-active-region for space and heat reasons No equipment to measure easily. See also: J.Franz, EMV, ISBN 978-3-8348-0893-6 100 W Ceramics X7R 10 W Murata, 100nf Murata, 1nf Murata, 10nf Tantalum, AVX, 33µF Murata, 2.2nf PCB, alone 1 W Impedance Z=|U|/|I| 0.1 W Total: 12 Tantal/4 ASIC’s + 17 ceramics + PCB 00.1 W No thrust in simulation 900 Coil like U to I phase shift 00 Capacitor like -900 1GHz 1MHz 1kHz Frequency PCB-layer Tantal Dominated by: ceramic

4. Technique for low frequency < 10kHz:Charge storage, V-regulator At end of layer, there is a bit of - space - cooling C2 C3 • GND-point definition: • Mechanical feasible • Granularity: One per (few) layer • Near most sensitive • Look for parasitic currents • e.g. capacitance+ voltage drop • in long layer • Voltage change • during train • Current change • in cable

5. Infrastructure with parasitic parameters Real Tantalum-C’s Power supply: Cto chassis(Toellner) Cable above metal support Inductance to support Parasitic LC (only return): 1cm 0.5m Current switch Current switch Parasitic elements increases currentpp a factor 5000 0 16µs 0 Slope is dis-/recharge during train Current in PE [A] Very small amplitude oscillation -0.5m -10µ 0ms 1ms 0µs 50µs Time after current switch Need: - Reasonably done infrastructure, e.g. small L’s, C’s - Electronics (e.g. p-filter) reducing sensitivity - Cable type: shield?, supply-return in one

6. Techniques for power supply system • Multichannel systems • - to keep supply/return currents near, • not using metal infrastructure to distribute • Floating per channel: Individual voltage drops • Low ripple: 5-10(20) mVpp • Should tolerate low frequency modulated loads • It is not too exotic, • But for 1500 layers , • best individual, • or in small geometrical nearby groups • Need a well adopted system. • On the market • are developments (partially) driven by research • CAEN, ISEG, WIENER and ?????? • ? • DC/DC-converters • Floating • Magnetic field • Low ripple. • Pulsed load • AHCAL • - has less stringent cable • requirements, • - not really needed. • - Multi-wire cables are an • option • Others might profit To far in the future for a survey ordedicated developments

7. Summary Items to look at: • ASIC’s: Can they limit rise/fall times? • Closing current loops in regions adequate for frequency? PCB design, charge storage, regulators • Where to locate heat production, if needed? • Real components: Passives and PCB’s • Infrastructure needs more care and collaborative work for different crafts Don’t disturb performance of others, I in own volume/infrastructure • GND-to-PE definition

8. Backup • Backup

9. What to look at: Frequency range • Switched Current sinks are likely: • ASIC’s switched themselves ON/OFF • for AHCAL barrel, total 3.4kA! • Frequency range to be looked at • High end by ASIC • - Optimize EMI vs. efficiency • ILC : 1ms-trains • CLIC : 0.2µs-trains • Low end is the ~ train-repetition • ILC: 5Hz • CLIC: 50Hz • With existing SPIROC: • 5Hz-few 100MHz Measured currents - AHCAL 36channel ASIC (SPIROC-2) - 1 pin of 3 parallel Current/pin [mA/pin] Probe DC-5MHz Time after switch [µs] 30mA Probe 30MHz-3GHz

10. Motivation Cooling generates inhomogeneity, material and risks Less dead materials: Thinner cables, less volume Duty cycles and possible gains for power and cooling: ILC 0.5% 1ms every 5Hz CLIC 105 0.2µs every 50Hz My work is based on CALICE-AHCAL, the barrel With power cycling aiming for 40µW/channel in active volume 4 million channels: 160Win the active volume end-of-active-area: 1540 layers each FPGA or ASIC much more their Side remark: Cooling type even for 160W, 1K increase: - air-cooling: 0.133m3/s or 5km/h @ large cross section 0.1m2 - water(liquid) cooling is what expect at the end-of-active-area.

11. What to look at: EMI in a Power Cycled System • Reference ground: • Need good definition • Any induced/applied current produces voltage drops • Separation between reference / power return / safety • or controlling currents • and keeping currents within “own” volume and instrumentation • Each sub-detector might need different switching and quite time return reference Safety. PE • Current loops • To do: • Controlling return currents • Keeping loops small • Avoid overlapping with • foreign components. • Capacitive coupling • To do: • Keep common mode voltage stable • Guide induces currents to source • Keep GND-reference closer • than foreigns Guideline: Avoiding emission avoids in most cases picking up of noise

12. Phase variations 100MHz-1GHz Resistor can dump resonant behavior Simulation 16´ 1.6W Each AC-coupled with real 100nF Reality - Not on the boards - No negative effects seen - ASIC’s do it themselves? - Easy for next generation to be safe. 10 Granularity Limit of simulation Only PCB and C’s Additional R-C’s 1 0.1 Impedance [Ohm] 0.01 +900 00 phase -900 G Frequency [Hz] VCC 1.6W Real C: 100nF Simulation: L-R-C

13. Voltage at ASIC: Measurement Reduced test setup: Control board, 1 interconnect, 1 board Definition of GND-point: - good for keeping sensitive SiPM’s stable - single connection to reduce currents in GNDPE system Parasitic parameters to be looked at: e.g. Capacitors - Currents in the GNDPE Due to voltage steps and stray capacitance: few mA/layer*1500layer - huge amount of steel, but to be kept in mind. parasitic C=13nF 2m2/Layer 1.3mm distance Stainless steel absorber = GNDPE GNDelectronics 4mV Default setup Supplyvoltage of ASIC (AC-component) [mV] Tantalum moved to control board Power on Command, step in IASIC Tantalum taken away Control electronics for layer Time [ns] Þ OK, even with extrapolation to 1500 layers low? Investigations of reason and improvements possible, to be watched

14. Technique to integrate Infrastructure 70pF/m from cable to support ASIC as switched current sink Not simulated 50m cable, 1mm2, on a cable support First view: Really small ! Just the standard: Cable on a metal support and every thing is OK? With 1500 layers of AHCAL: IPE=120mA Really small, but not all parasitic effects! Don’t be too reluctant in EMI-rules Current induced into GNDPE nA 0 -40 -80 -120 -160 Current per layer Simulation of cable 0 1 2 3 4 5 [ms] 6 time

15. Measurement: Current in Supply Cable Reduced test setup: Control board, 1 interconnect, 1 board, Short cable to laboratory supply Preamplifiers ON ADC’s ON Work bench settings Without input filter with input filter t=10ms Current per 1/18 layer in supply cable [mA] Input filter important to lower amplitude fluctuations and remaining frequencies within cable Important: EMI-crosstalk to others Frequencies are low Electronics like to have larger t to smoothen further Û Mechanics easier in service-hall Control electronics for layer