Upgrade calo FE review Comments : Digital part

1. Upgrade calo FE reviewComments : Digital part This is just a support to start the discussion • Friday, 20 September 2013 Calorimeter upgrade meeting Olivier Duarte

2. FPGA Choice • Point (2) : • Open questions on the architecture of the FEB and the CB • a single FPGA could do the job of the "Trigger-PGA" and the job of the "Control-PGA” • New target SmartFusion2 flash FPGA from MicroSemi • At the moment we target A3PE 1500 FPGA for the FEPGA of the FE block (FEB). It’s a compromise between radiation tolerance, price, number and standart IOs and internal resource in the chip. • A single FPGA for “Trigger and Control” Why not ! • It will be define when we define precisely the architecture of the board ! • The new family FPGA SmartFusion2 include specifiques functions as SerDes, Arm processor, etc (We haven’t need of the function !). But “Buffers Implemented with SEU Resistant Latches on the DDR bridge SPI FIFO”. Price and availability? • Need more investigation on this new family ! Calorimeter upgrade meeting

3. SLVS-LVDS translation • Point (3) : • The need for SLVS-LVDS translation must be evaluated. The GBTX is specified to receive LVDS signals. Basic tests from CMS indicate that the A3PE1500 can accept SLVS signals, but these should be verified with more detailed tests. • The prototype FEB and CROC board will be used to test this compatibility of the A3PE and SLVS Calorimeter upgrade meeting Friday, 20 September 2013

4. Clock distribution on the backplane • Point (6) : • The clock distribution architecture in the FEB crate should be investigated. • Usage of buffers or translators within FPGAs might create additional jitter or destroy fine phase/latency control. • If it is possible to go directly from the GBTX chip to the FPGA or analog chip via the backplane (with no significant degradation of signal in terms of jitter) than that should be the cleanest option. • On the board it’s possible to go directly from the GBTX chip to the FPGA . • On the backplane we will used LVDS, It will be tested with the prototype board (FEB and CROC) • Even if we want to use SLVS on backplane, it’s necessary to use buffer (vey low jitter!) between the board and the backplane. Calorimeter upgrade meeting

5. First prototype with mezzanine for GBTX and SCA • Point (7) : • It was suggested to design the first prototypes to have mezzanines or similar so that external chips (GBT-SCAs or GBTXs) can be plugged when available and tests can still be performed while waiting for those chips to be available. • The idea is to do the prototype FEB and CROC with the footprint describe in the GBT datasheet (BGA) • Very difficult to implement a mezzanine (area, type of connectors, ...) • It’s possible to start the tests of the board without GBT solder on the PCB ! Calorimeter upgrade meeting

6. No mezzanine for data transmission • Point (8) : • In the initial version of the new design, event data serializers and associated optical drivers were located on mezzanines. Due to the lack of manpower for following this option, it might be wise to come back to a direct implementation of these components on the front-end boards. • Increase the intrinsic cost of the front-end boards • No mezzanine, event data serializers and asociated optical drivers will be located on the FEB and on the CROC . • To separate the cost of the links (serializers + optical drivers/receivers + fiber optics) from that of the boards and to have a separate funding  See Frédéric Calorimeter upgrade meeting

7. Firmwaredownload by Slow Control • Point (10) : • In-situ programming of the FPGAs should be investigated in more detail. This assumes that the bit-stream can be transmitted via the GBT-SCA. • The power requirements for the flash programming should be clarified and incorporated into the system. • Completely agree with this point • In fact we want to reuse and adapt the development of the CMS team • What is the situation of this development ? • Completely agree with this point Calorimeter upgrade meeting

8. Spare Calorimeter upgrade meeting

9. Front-end board global architecture E-Port E-Port 8 Channels Front-End Block 2 Channels analog part GBTX (One way) 2 Channels analog part • ACTEL FPGA (A3PE1500) • Reprogrammable • Rad tolerant E-Port 2 Channels analog part E-Port 2 Channels analog part GBTX 4 One way links per FEB for DAQ Analog chip clip • Functions: • Pedestalsubtraction • Data formatting • Compute trigger info (BXID, Calo hit , EE address,…) Buf.  12b ADC (2 cha.) Network Controller PMT General Ctrl General Ctrl Slow Control …… 12m cable Delay Line clip Detector cells Buf.  112b @ 40MSPS User Buses : Clk manager Clk manager In Ref E-port output at 80 MHz {I2C, //, SPI, JTAG, 12bADC, …} : Clk[7:0] Clk[7:0] In Ref In Ref CLK_Ref GBTX (One way) Trigger - PGA (ACTEL - A3PE family) Clock_Feb(n) Uplink Uplink {From Ctrl. Board through 3U Backplane} GBTX E-Port LVDS-SLVS translator Control - PGA (ACTEL - A3PE family) E-Port (FPGA, Buffer, …) On board bus 1 One waylink per FEB for LLT Down- link Down- link E-Port E-Port Power Supply : E-Port DC-DC Converter 80b @ 40MSPS 32 Channels CLK_Ref Power Supply protection : (Delatching control) ECAL-HCAL FEB Translator E-Port FPGA, Buffer, … GBT-SCA Input E-port LVDS ok Delatching Control fromCtrl_Board (throughBackplane) Slow control from Control Board(throughBackplane)

10. Front-end Board architecture Clock from CROC Through backplane LVS-SLVS translator New FEB 32 Channels Clock_Feb(n) E-Port 1 One waylink per FEB for LLT E-Port E-Port E-Port Clk[7:0] In Ref Clk manager Network Controller General Ctrl 4 One waylink per FEB for DAQ ACTEL FPGA (A3PE1500) PM Analog FE part (8 Channels) GBTX User Buses : 4 GBTX (One way) {I2C, //, SPI, JTAG, 12bADC, …} • Technology • Analog Front-end • ASICS (Barcelona) • Discret components solution • Digital Part • Actel FPGA, A3PE family Slow control from CROC Through backplane Translator SLVS-LVDS E-Port SCA Uplink FPGA, Buffer, … Down- link • GBT on board • On the new Calorimeter FEB • 4 GBTX chip (one way) for Data • 1 GBTX chip (one way) for LLT • 1 SCA chip (FEB Ctrl/Cmd)

11. CROC architecture • Why keep the CROC • Provide the distribution of the synchronouscommands signal (Channel B, …) to the FEB inside FE Crate • Provide Slow Control distribution • Provide Clk distribution Clk[0] E-Port One GBTX master E-Port SLVS-LVDS translator Clock distribution to FEB through backplane In Ref Clk[7:0] Clk manager E-Port E-Port x (18) E-Port_TVB E-Port_FEB Network Controller General Ctrl 2 bidirlink Translator SLVS-LVDS GBTX Buffer FPGA, Buffer, … E-Port SCA _NewCROC 2 bidirlink 2 GBTX E-Port SCA User Buses : E-Port SCA_NewCROC {I2C, //, SPI, JTAG, 12bADC, …} Uplink Down- link New CROC 1 SCA LHCb AMC40 firmware workshop • GBT on board • On new CROC board • 2 GBTX (one master) chip with bidirectional optical fiber (right side and left side of FE crate) • 1 SCA chip (CROC Ctrl/Cmd)