B6: Jitter, Power Integrity, and Proper PDS Design For FPGA Systems

1. B6: Jitter, Power Integrity, and Proper PDS Design For FPGA Systems Tim Jaynes 9/10/2003

2. Agenda • Jitter: A brief discussion and it’s relationship to Power Integrity • Power Integrity Concerns • Power Distribution System Design • Keeping it Clean • Conclusion

3. Motivation • Jitter from power supply noise has become increasingly important as timing margins shrink and FPGAs integrate more fabric and more sensitive IP. • A well designed Power Distribution System is the key to overcoming the mounting challenges.

4. Jitter, a Brief Background • Period Jitter = The change in clock period (from ideal) over many samples. • Cycle-to-Cycle Jitter = Difference in the period jitter on two consecutive periods (over many samples of consecutive periods).

5. Jitter, still a Brief Background • Sequence of measured periods: • Period Jitter = +(the largest period) / -(the smallest period) [from Ideal] = +(10.1ns-10ns) / -(10.0-9.9ns) • = +(.1ns) / -(.1ns) or +/-100ps • Cyc-to-Cyc Jitter = +(the largest positive consecutive period) / -(the largest negative consecutive period) • Consider all cases independently and in sequence: • 10.0 to 10.1 (100ps positive change) • 10.1 to 9.9 (200ps negative change) • 9.9 to 10.0 (100ps positive change) • 10.0 to 9.9 (100ps negative change) • the largest positive consecutive period = 100ps • the largest negative consecutive period = 200ps •  Cyc-to-Cyc Jitter = +100ps / -200ps [10.0ns, 10.1ns, 9.9ns, 10.0ns, 9.9ns]

6. Noise to Jitter Conversion: Fundamentals Internal PWR or GND Rail Core CLK at BUFG Input Core CLK at BUFG Output after many samples • Noise can move the switching threshold point of a transistor (or in our case a Bufg). • The greater the noise (GND bounce or VCC ripple) the greater the potential jitter.

7. Noise to Jitter Conversion: Fundamentals Internal PWR or GND Rail A Core CLK at BUFG Input A’ B • Uncertainty of threshold reference (A from power supply noise) determines jitter • The buffer can switch (threshold) anywhere in this region (A’) • The slower the rise time the more opportunity is presented to PWR noise • Amount of jitter directly proportional to the magnitude of the noise/ripple/GND bounce • B (jitter) = A (noise) * dt/dV

8. Vcc Gnd V2/V2P Global Clock Drivers BUFG Generic representation of the Global Clock Network • There can be as many as 3 different BUFG drivers a global clock will pass through • This means 3 times that PWR/GND noise can move the clock (accumulate jitter)

9. Solution? Minimize power supply noise by paying careful attention to POWER INTEGRITY.

10. Where’s the problem? • Power supply noise DOES NOT come from the Vreg • Noise comes from the devices themselves • Digital circuits are noisy! • Source of all PDS noise: • Transient currents flowing through parasitic inductances

11. Providing a better path • In order to avoid the inductance of the whole distribution system we use bypass capacitors to provide quick energy to the FPGA. This provides a low impedance path for high frequency currents. But how much is enough?

12. PDS Design for FPGAs • One capacitor per Vcc pin • Yes, EVERY Vcc pin – Vccint, Vcco, Vccaux, Vref • Within the total count for each supply: • Allocate some in each frequency range • 3% 680 uF • 7% 2.2 uF • 15% 0.22 uF • 25% 0.047 uF • 50% 0.001 uF • Power planes and/or sandwiches are a must

13. Nobody’s Perfect • Even with the addition of bypass capacitance there are still sources of inductance in the current loop which can cause power supply noise. • Plane inductance • Determined by the shape of the plane (pH/sq) and dielectric thickness • Bypass capacitor parasitics • Capacitor Mounting • Solder land, trace to via, *via itself*

14. Via parasitic can be biggest contributor • Board thickness is critical factor if caps on the bottom • 62mil finished thickness -- typical LVP = 1.5nH • 127mil finished thickness -- typical LVP = 3.2nH Vias -- the silent killer • Mounted Capacitor Parasitics • LC Capacitor self-inductance 0.7nH - 1.2nH • LLD, LLC Solder land inductance of device and cap 0.1nH - 0.4nH • LP Power plane inductance 0.03nH - 0.4nH • LVP Via pair inductance 0.3nH - 3.2nH *Inside device, Package Grounds are ~45pH each, Vcco’s ~150pH each

15. Capacitor Placement • High frequency energy needs to be provided a short distance from the part. • This is important not only in minimizing the current loop size, but in ensuring efficient energy delivery. • Rule of thumb is to place capacitors within 1/40 of the wavelength associated with their resonant freq. • Ranges from just over 1 inch for .001 uF capacitors to over 100 inches for the larger tantalum capacitors.

16. Try Before You Buy • Simulation is needed to view network impedance profile • Should cover frequencies from 500 kHz to 800 MHz • Impedance should be low and flat over this range

17. Must have 1 GHz or better scope Must have 1 GHz or better probes Probe power vias on back of board Use infinite persistence mode Then Build and Measure • Noise on all supplies should be less than 10% of nominal • Measure with a fast oscilloscope

18. How to Measure Noise • Direct Measurement - views voltage & noise at PCB PDS • Backside vias • MAKE SURE NO CAPACITOR IS PRESENT! • Measure VCC pin against GND pin • Spy-hole - views voltage & noise at FPGA PDS • Measure through User I/O in bank tied to supply of concern • Two unused outputs: set one to ‘1’, set one to ‘0’, drive strong* • If trace is present, use 50 ohm termination resistor(s) • Measurements • ‘1’ output against ‘0’ output • ‘0’ output against local PCB PDS GND • Compare *drive strong = use a high drive-strength output driver like LVCMOS24

19. measure here measure here Noise on PCB PDS (somewhat irrelevant to FPGA operation, but can tell you if someone else (another device) is muddying the water) Noise at Die -- FPGA PDS (what the fabric sees) measure here Ground Bounce (how much noise is between PCB PDS and the FPGA die) Spy-Hole vs. Backside Measurements PCB PDS PCB vias, planes Backside Via PKG Bondwire or pkg route Package Ball DIE IO Output IOB 1 + V IOB 0 IO Output Package Ball Bondwire or pkg route Backside Via PCB vias, planes PCB PDS

20. Conclusion • Power Integrity concerns are a serious issue in FPGA system design • Jitter is becoming more of a factor • Good PDS Engineering is essential • Use lots of capacitors • Get trained, stay current, and read the fine print!

21. Appendix IREFERENCES • Howard Johnson and Martin Graham, High Speed Digital Design: A Handbook of Black Magic, Prentice Hall, New Jersey, 1993. • Mark Alexander, XAPP623 PDS Design: Using Bypass/Decoupling Capacitors, Xilinx Appnote, 2002. http://www.xilinx.com/xapp/xapp623.pdf

22. Appendix IIUSEFUL RESOURCES • Signal Integrity Central – Xilinx site with links to all Xilinx SI literature http://www.xilinx.com/signalintegrity • PCB Checklist – Checklist with all pertinent items and explanations, links http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=si_pcbcheck • SI Reflector – Good discussion list with its share of gurus Si-list-request@freelists.org, archives athttp://www.freelists.org/archives/si-list • Your local EMC Society – Excellent resource to help you stay current http://www.ewh.ieee.org/soc/emcs • SI Training from qualified experts – Fast path to success http://www.gigatest.com Eric Bogatin http://www.signalintegrity.com Howard Johnson http://www.speedingedge.com Lee Ritchey http://www.ultracad.com Doug Brooks

23. Appendix III:BASIC DECOUPLING RULES • Use small capacitor packages • Parasitic L is proportional to pkg. size • Use largest value in a given package • L is dominated by pkg, so maximize C • Connect cap lands directly to planes • NEVER share cap vias • Keep trace between land and via short!! • Benefit of small package is lost otherwise