1 / 14

The Abstract simulator

The Abstract simulator. Simulator/Simulation Concepts. Simulator: responsible for executing a model’s dynamics (resented as instructions) in a given formalism. Abstract simulator: a characterization of what needs to be done in executing a model’s instructions atomic simulator

susane
Download Presentation

The Abstract simulator

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. The Abstract simulator

  2. Simulator/Simulation Concepts • Simulator:responsible for executing a model’s dynamics (resented as instructions) in a given formalism. • Abstract simulator: a characterization of what needs to be done in executing a model’s instructions • atomic simulator • coupled simulator • Simulation engines: enforce particular realizations of abstract simulator • Simulations can be executed as: • Sequential • Parallel • Distributed (sequential/parallel) • Real-Time

  3. Standard DES mechanisms Time Event routine t1 E1 : : < Event list > Transition: event generation until event listempty • Simulationperformance : event list management • event list: insert, delete, location • search time: not constant (solution : priority queue implementation heap)

  4. Abstract simulation : Hierarchical simulation (scheduling) algorithm C:ABC ABC C:AB AB S:C C S:A A S:B B • (i) Concept : separation of control (scheduling) algorithm from data(model) User’s spec System’s simulation algorithm request Ack Passive agent (data) server Active agent (control) client S : C : simulator for model C (simulation algorithm) C: AB : Coordinator for model AB (simulation algorithm) (ii) Hierarchical scheduling  No global event list

  5. Processors: two types of simulation entities (iii) Two classes of simulations  simulator class Associated with atomic DEVS (int, ext, ta, ) invoke  coordinator class Associated with coupled DEVS Event routing Hierarchical scheduling < GEN-BUF-PROC model > <BUF-PROC model> out in out in out out GEN BUFFER PROC done

  6. Simulation entities example

  7. Message passing • External Events • Internal Events

  8. Types of messages involved and their interaction C: GENBUFPROC GENBUFPROC (x, t) (*, t) (x, t) (*, t) (done, tN) (done, tN) C: BUFPROC BUFPROC S : GEN GEN (x, t) (*, t) (x, t) (*, t) (done, tN) (done, tN) S : BUF BUF S : PROC PROC  (x, t) : external input event arrival at time t  (*, t) : internally-generated event at time t that notifies the scheduled time is completely elapsed  (done, tN) : synchronization event generated at time tN that notifies the next scheduled time is tN

  9. Simulator and Coordinator activities Wait (x, t) Simulator for AM (done, tN) (x, t) (*, t) (*, t) M:ext (done, tN) M:  M:int When receive (x,t), invokeextand ta setting When receive (*,t), invokeint, and ta setting ta SELECT needed Wait (*, t) Route(*,t) imminent(i*) component (x, t) (x, t) Coordinator for CM (done, tN) (*, t) Route (x,t) wait till done (done, tN) (done, tN) schedule Wait i* done and (x,t) from i* done Minimum tN

  10. Coordinator activities (*, t) Wait Route(*,t) imminent(i*) component (x, t) tL Coordinator tN (done, tN) (x, t) (done, tN) Route (x,t) wait till done schedule Wait i* done and (x,t) from i* done (*, t) When receive (*,t) if t = tN then find component(s) with tN select one i* send (*,t) to i* wait response: (yi, port) translate yi* to x send x to its influencees wait i* and its influencees done tL := t tN := min{tNi | i: i* + its influencees } send (done, tN ) to upper level coordinator else error When receive (x,t) if tL t  tN then send (x,t) to connected component(s) wait all component(s) done tL := t tN := min{tNi | i: component} send (done, tN ) to upper level coordinator else error

  11. Coordinator: example GEN+BUF+PROC BUF+PROC out in GEN BUF PROC out in out done Root SELECT GEN C : G+B+P G B P 1 2 3 4 5 6 7 8 G B S : G C : B+P B P ta(BUF) : 2 1 3 2 1 ta(PROC) : 1 2 1 3 2 S : B S : P G P

  12. Coordinator: example (contd.) t S : GEN S : BUF S : PROC C : B+P C : G+B+P ROOT (done, tN=1) 0 2 1 3 (*, 1) t = 1 2 3 1 (s) int(s)  (6) ext(s) (5) Route: (4) Route: ta = 1 ta = 2 S:BUF C:B+P tN=3 schedule tN=2 tN=3 (done, 2) 2 1 3 t = 2 (*, 2) 2 3 1 (s) int(s)  ext(s) ta = 2 ta = 1 schedule tN=4 tN=3 tN=3 (done, 3) 2 1 3 (*, 3) t = 3 2 3 1 (S) int(s)  ext(s) ta = 1 ta =1 schedule tN=4 tN=4 tN=4 (done, 4) 2 1 3 (*, 4) t = 4 2 3 1 (s) int(s)  ext(s) ta = 2 ta = 2 schedule tN=6 tN=4 tN=4 (done, 4) 2 1 3

  13. Note on abstract simulator 1. Modeler has no responsibility in time control No worry about execution sequence (No explicit initial state) 2. Separation of characteristic functions in modeling simplicity, reusability 3. Close under coupling operation Example of 2 : Buffer BUF ext :X  Q  S int : S  S  : S  Y ta : S  R+0, reusable FIFO (First-in, First-out) LIFO (Last-in, First-out) insert delete insert delete FIFO LIFO

  14. Generator CD++ - Simulation Mensaje I / 00:00:00:000 / Root(00) para top(01) Mensaje I / 00:00:00:000 / top(01) para gen(02) Mensaje D / 00:00:00:000 / gen(02) / 00:00:00:000 para top(01) Mensaje D / 00:00:00:000 / top(01) / 00:00:00:000 para Root(00) Mensaje * / 00:00:00:000 / Root(00) para top(01) Mensaje * / 00:00:00:000 / top(01) para gen(02) Mensaje Y / 00:00:00:000 / gen(02) / out / 0.000 para top(01) Mensaje D / 00:00:00:000 / gen(02) / 00:00:03:324 para top(01) Mensaje Y / 00:00:00:000 / top(01) / out / 0.000 para Root(00) Mensaje D / 00:00:00:000 / top(01) / 00:00:03:324 para Root(00) Mensaje * / 00:00:03:324 / Root(00) para top(01) Mensaje * / 00:00:03:324 / top(01) para gen(02) Mensaje Y / 00:00:03:324 / gen(02) / out / 1.000 para top(01) Mensaje D / 00:00:03:324 / gen(02) / 00:00:02:308 para top(01) Mensaje Y / 00:00:03:324 / top(01) / out / 1.000 para Root(00) Mensaje D / 00:00:03:324 / top(01) / 00:00:02:308 para Root(00) Mensaje * / 00:00:05:632 / Root(00) para top(01)

More Related