Introduction to VLSI: From Basics to Implementation

1. Introduction to VLSI(ECE 349b) Wei Wang Electrical and Computer Engeering Dept. The University of Western Ontario London, ON, Canada Winter 2003

2. Lecture 1 Course Introduction Jan. 6 2003

3. General 1. Welcome remark • Definition of VLSI • Importance of VLSI

4. Course Requirement • Expectations • Academic & industry • Rules • Attendance & Assignment • Lab • Midterm & final

5. Information • Text book in library: • Call no.: TK7874.65.W65 2002 • Class notes and lab manual: • Ftp sun30.engga.uwo.ca • Username: ece480a • Password: ec.48.EC

6. Information (cont’d) • Labs: • 2 UNIX labs: EC 2135 (Weeks of Feb. 4 and 18) • Two PC labs: EC1000 (Weeks of Mar. 4 and 18) • (Tuesday, Wednesday and Thursday morning) • Assignments: • Two weeks from the post date • Drop-off box : in front of lab

7. Wei Wang Office: EC 1006 Office hours: Monday and Wednesday 2:00 to 3:00 pm Email: wwang@eng.uwo.ca

8. Overview • Why VLSI? • Moore’s Law. • ASIC: Abstraction and Hierarchy. • FPGA: cheaper ASIC

9. VLSI and you • Microprocessors: • personal computers; • microcontrollers. • DRAM/SRAM. • Special-purpose processors. • Many other applications: telecom, DSP,etc.

10. Moore’s Law • Gordon Moore: co-founder of Intel. • Predicted that number of transistors per chip would grow exponentially (double every 18 months). • Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

11. Moore’s Law plot

12. Lecture 2 Overview of VLSI Jan. 8 2003

13. Overview • Why VLSI? • Moore’s Law. • ASIC: Abstraction and Hierarchy. • FPGA: cheaper ASIC

14. ASIC and FPGA • Application-specific integrated circuit design • Field programmable gate array • ASIC: 2 UNIX labs (our main focus) • FPGA: 2 PC labs

15. ASIC • Top-down approaches

16. Levels of abstraction • Specification: function, cost, etc. • Architecture: large blocks. • Logic: gates + registers. • Circuits: transistor sizes for speed, power. • Layout: determines parasitics.

17. English Throughput, design time Executable program Function units, clock cycles function Sequential machines cost Literals, logic depth Logic gates nanoseconds transistors microns rectangles Design abstractions specification behavior register- transfer logic circuit layout

18. English Synopsys VHDL/verilog (schematic) Gate netlist Cadence (schematic) Transistor netlist CAD Tools specification behavior register- transfer logic circuit layout

19. ASIC: Hierarchical name • Interior view of a component: • components and wires that make it up. • Exterior view of a component = type: • body; • pins. cout Full adder sum a b cin

20. Add2.a Add1.a ASIC:Instantiating component types • Each instance has its own name: • add1 (type full adder) • add2 (type full adder). • Each instance is a separate copy of the type: cout Add2(Full adder) Add1(Full adder) sum sum a a b b cin cin

21. Net list: net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet Net lists and component lists

22. Component hierarchy top i1 xxx i2

23. Hierarchical names • Typical hierarchical name: • top/i1.foo component pin

24. Layout and its abstractions • Layout for dynamic latch:

25. Stick diagram

26. Transistor schematic

27. Mixed schematic inverter

28. Lecture 3 Overview of VLSI (cont’d) Jan. 10 2003

29. Overview • Why VLSI? • Moore’s Law. • ASIC: Abstraction and Hierarchy. • FPGA: cheaper ASIC

30. Characteristics of ASIC • Expensive • Many cycles of design: Simulation, synthesis • Design for testing (DFT)

32. Layout of ASIC Pentium IV Technology: 0.13 um Area: 35 mm square Speed: 2.2GHz Power: 55 W

33. English Throughput, design time Executable program Function units, clock cycles function Sequential machines cost Literals, logic depth Logic gates nanoseconds transistors microns rectangles Design abstractions specification behavior register- transfer logic circuit layout

34. English Synopsys VHDL/verilog (schematic) Gate netlist Cadence (schematic) Transistor netlist CAD Tools specification behavior register- transfer logic circuit layout

35. Characteristics of FPGA • Programmability • Simulation, synthesis • Test

37. Layout of FPGA

38. Top-down vs. bottom-up design • Top-down design adds functional detail. • Create lower levels of abstraction from upper levels. • Bottom-up design creates abstractions from low-level behavior. • Good design needs both top-down and bottom-up efforts.

39. English Throughput, design time Executable program Function units, clock cycles function Sequential machines cost Literals, logic depth Logic gates nanoseconds transistors microns rectangles Design abstractions specification behavior register- transfer logic circuit layout

40. English Xilinx Foundation tools VHDL/verilog (schematic) Gate netlist (schematic) Transistor netlist CAD Tools specification behavior register- transfer logic circuit layout

41. Contents of the Course ASIC FPGA • Transistor and Layout • Gate and Schematic • Systems and VHDL/Verilog

42. Contents of the Course (cont’d) 2 ASIC labs 2 FPGA labs • Transistor/Layout • Gate and Schematic • Systems/VHDL (Cadence) (Xilinx Foundation) (Synopsys)

43. The Future Is Not What It Used To Be

44. Future of VLSI • Nanotechnology • Biotechnology • Information technology