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This overview covers the sequencing of instructions in digital hardware systems, including an example of adding the contents of two registers and placing the result in a third register. It also discusses instruction types, elements of the control unit, instruction execution, data paths, and memory operations.
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Overview • Last lecture • Tri-state gates and Open-collector wire-AND’s • Digital hardware systems • Register files. Memory • Today • Instruction Execution CSE 370 – Winter 2002 – Comp.org 1 - 1
Instruction sequencing • Example – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz) • Step 1: get the ADD instruction from memory into an instruction register (IR) • Step 2: decode instruction • instruction in IR has the code of an ADD instruction • register indices used to generate output enables for registers Rx and Ry • register index used to generate load signal for register Rz • Step 3: execute instruction • enable Rx and Ry output and direct to ALU • setup ALU to perform ADD operation • direct result to Rz so that it can be loaded into register CSE 370 – Winter 2002 – Comp.org 1 - 2
Instruction types • Data manipulation instructions • arithmetic: add, subtract, increment, decrement • multiply,divide • shifts, bit-string ops, complements, etc. • floating point? usually a separate datapath • operands (data) may be from memory, from registers, or “immediate” • Data staging instruction • load/store data to/from memory • register-to-register move • Control instructions • conditional/unconditional branches in program flow • subroutine call and return • A different categorization of instructions: no-operands, 1 operand, etc. CSE 370 – Winter 2002 – Comp.org 1 - 3
Elements of the control unit (aka instruction unit) • Control unit inputs/outputs • outputs control signals data path • inputs from data path used to alter flow of program (test if zero) • Standard FSM elements • state register • next-state logic • output logic (datapath/control signaling) • Moore or synchronous Mealy machine to avoid logic loops unbroken by FF • Plus additional "control" registers (but they are in the data path) • instruction register (IR) • program counter (PC) CSE 370 – Winter 2002 – Comp.org 1 - 4
Instruction execution • Control state diagram (high level of abstraction)) • reset • fetch instruction (from memory) • decode • execute (perform operation) • Instructions partitioned into three classes • branch • load/store • register-to-register • Different sequence throughdiagram for eachinstruction type Reset Init InitializeMachine FetchInstr. Load/Store XEQInstr. Branch Register-to-Register Branch Taken BranchNot Taken Incr.PC CSE 370 – Winter 2002 – Comp.org 1 - 5
Cin Ain FA Sum Bin Cout Ain Sum HA Bin Cout HA Cin Data path (hierarchy) • Arithmetic circuits constructed in hierarchical and iterative fashion • each bit in datapath is functionally identical • 4-bit, 8-bit, 16-bit, 32-bit, 64-bit datapaths CSE 370 – Winter 2002 – Comp.org 1 - 6
A B 16 16 Operation 16 N S Z Data path: Arithmetic Logic Unit • ALU block diagram • input: data and operation to perform • output: result of operation and status information CSE 370 – Winter 2002 – Comp.org 1 - 7
16 REG AC 16 16 OP N 16 Z Data path (ALU + registers) • Accumulator (AC or A register) • special register found in many (old) architectures • one of the inputs to ALU • output of ALU stored back in accumulator • One-address instructions • operation and address of one operand • other operand and destinationis accumulator register • AC <– AC op Mem[addr] • "single address instructions”(AC implicit operand) • Multiple registers • part of instruction usedto choose register operands CSE 370 – Winter 2002 – Comp.org 1 - 8
CO CO ALU CI ALU ALU CI AC AC AC rt R0 rs rt rd rd rs rt rd R0 rs R0 frommemory frommemory frommemory Data path (bit-slice) • Bit-slice concept – iterate to build n-bit wide datapaths 1 bit wide 2 bits wide CSE 370 – Winter 2002 – Comp.org 1 - 9
Data path: memory interface • Two Possible Memory Arrangements • separate data and instruction memory (Harvard architecture) • two address busses, two data busses • single combined memory (Princeton architecture) • single address bus, single data bus • Common concepts • Memory Address Register (MAR): tells memory unit which address to read/write • Memory Data Register (MDR): contains data to/from memory • MAR and MDR might be separate registers labeled as such, or might be existing registers used for the purpose CSE 370 – Winter 2002 – Comp.org 1 - 10
Memory operations • For a data read • Load MAR with address of word to be read (from IR for our very simple machine; from output of ALU for more complex ones) • Apply the read command; data is in MDR • Transfer MDR into Register (in more complex machines in one register of the register files) • For an instruction read • Load MAR with address of instruction (from PC) • Apply the read command; instruction is in MDR • Transfer MDR into IR • For a data store • Load MAR with address of word to be written (from IR) • Load MDR with contents of the word to be written (from AC) • Apply the write command CSE 370 – Winter 2002 – Comp.org 1 - 11
Block diagram of processor • “Register transfer view” of Princeton architecture • emphasizes which register outputs are connected to which register inputs • arrows represent data-flow, other are control signals from control FSM • load control for each register • MDR/MAR not always there (use tri-sate gates) load path 16 REG AC rd wr MDR storepath 16 16 data Data Memory (16-bit words) OP addr N 8 Z ControlFSM MAR 16 IR PC 16 16 OP 16 CSE 370 – Winter 2002 – Comp.org 1 - 12
load path 16 REG AC rd wr storepath 16 16 data Data Memory (16-bit words) OP addr N 16 Z ControlFSM 16 IR PC data Inst Memory (8-bit words) 16 16 OP addr 16 Block diagram of processor • Register transfer view of Harvard architecture • arrows represent data-flow, other are control signals from control FSM • load control for each register CSE 370 – Winter 2002 – Comp.org 1 - 13
CSE370 processor data-path and memory memory has only 255 wordswith a display on the last one • Princeton architecture • Register file • Instruction register • PC incremented through ALU • Modeled afterMIPS rt000(used in 378textbook byPatterson &Hennessy) • really a 32 bitmachine • we’ll do a 16 bitversion CSE 370 – Winter 2002 – Comp.org 1 - 14