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Status of the electronic systems of the MEG Experiment

This document provides an update on the status of the electronic systems of the MEG Experiment, including the HV, Splitter, and Trigger, along with milestones and expected next steps.

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Status of the electronic systems of the MEG Experiment

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  1. Status of the electronic systems of the MEG Experiment

  2. Topics • HV • Splitter • Trigger • Domino Ring Sampler

  3. HV • Original design works +- 0.2V @ 2400V • Microcontroller crashes if HV load changes quickly • Redesign started in Nov. ’03 • Improved sensitivity 16-bit DACs, 24-bit ADCs • (linear LTC2600 , analog device AD7718) • Faster microcontroller for 4 channels • (silabs C8051F310) • HV part optically decoupled from microcontroller • Communication always through the MSCB • Prototype in March ‘04

  4. Splitters Milestones • End of sep 2003:2-channels card built. • End of oct 2003:4-channels card prototype built. • Half of nov 2003: 4 x 4-channels cards with minicrate and power supply built and tested at PSI. • End of nov 2003: test at PSI.

  5. diff out out out Splitter in/out 4 splitter boards with: • 4 inputs50 Ω impedance (PMT input) • 4 x 2 outputs single-ended large bandwidth (DRS board and Monitor) • 4 outputs differential reduced-bandwidth (Trigger) • 1 adder sum of the 4 inputs (Trigger) in adder

  6. Splitter Electrical Characteristics • Based on Analog Device IC AD8009 and AD8138 • Gain of x1 (modified to x10 at PSI) • Integral non-linearity<6% (5.5% typical), between 40 and 130 mV input signal; • Channel to channel crosstalk<0.2% (0.1% typical) between 40 and 200 mV input signal • Rise time<1.5ns (1.2ns typical) Gain=10

  7. Timing comparison (channel F9) TDC (ns) Photoelectrons Photoelectrons TDC (ns) TDC (ns)

  8. Next steps • Adding single channel kill control • Adding test input • Increasing card density using CRG 0603 size components

  9. Expected Trigger Rate Accidental background and Rejection obtained by applying cuts on the following variables • photon energy • photon direction • hit on the positron counter • time correlation • positron-photon direction match The rate depends on RRe+ R2

  10. The trigger implementation Digital approach • Flash analog-to-digital converters (FADC) • Field programmable gate array (FPGA) Final system • Only 2 different board types • Arranged in a tree structure on 3 layers • Connected with fast LVDS buses • Remote configuration/debugging capability Prototype board Check of: • the FADC-FPGA compatibility • chosen algorithms • synchronous operation • data transmission

  11. LVDS Rec Analog receivers 16 x 10 PMT FADC FPGA 16 Clock Sync Trigger Start Out 4 4 16 16 48 Control CPLD 4 3 48 4 48 Sync Trigger Start Sync 2 boards Spare in/out Type0 Type0 VME Trigger Start LVDS Trans Trigger prototype board : Type 0 • VME 6U • A-to-D Conversion • Trigger • I/O • 16 PMT signals • 2 LVDS transmitters • 4 in/2 out control signals • Complete system test Board Type0

  12. The boardType0 control signals. LVDS transm. Differential drivers PMT inputs FPGA FADC LVDS receiv. configuration EPROMS package error solved with a patch board

  13. Prototype system Two identical Type0 boards Board 0 Board 1 Ancillary board Clock, sync, trigger and start distribution LVDS connection

  14. Circ. buff Circ. buff Circ. buff Circ. buff Diff. driver Diff. driver Proc. Algor. Proc. Algor. Fadc Fadc LVDS Tx LVDS Tx Proc. Algor. Proc. Algor. LVDS Rx LVDS Rx Circ. buff Circ. buff Circ. buff Circ. buff Board 1 Prototype system configuration input output 16 PMT Board 0 16 PMT input output LVDS in final

  15. Prototype system tests • Debugging of the first board Type0 in Pisa • A minor error fixed • System assembled at PSI in Nov. ‘03 • 100MHz synchronous operation • Negligible transmission error rate • Satisfactory operation of the analog interface • Connection with the Large Prototype • PMT from #0 to #31 • Collected data • Alpha • Led • 0

  16. Alpha Amplitude [mV] Input cyclic-buffer board 1 Time [10 ns]

  17. LED Amplitude [mV] Time [10 ns]

  18. 0 Amplitude [mV] Time [10 ns]

  19. Internal trigger Pulse time Output cyclic-buffer board 0 Input cyclic-buffer board 0 Amplitude [mV] Amplitude sum Index of Max Max. Amplitude (2) Time [10 ns]

  20. LVDS transmission Pulse time Amplitude [mV] Output cyclic-buffer board 1 LVDS input cyclic-buffer board 0 Amplitude sum Index of Max Max. Amplitude (2) Time [10 ns] 7 clock cycles delay

  21. Example of data comparison • 0 data • Charge spectrum • Only 32 PMT

  22. Further works • Hardware • JTAG programming/debugging through VME by modifying the Type0 • Block transfer in A32D16 format (VME library to be modified) • Final characterization on linearity, crosstalk … • Analysis • Alpha, Led and 0data to extensively check the algorithms Conclusions The prototype system met all requirements It is available to trigger the LP in future beam tests

  23. Final system • Trigger location: platform • Spy buffers to check the data flow are implemented • JTAG programming/debugging through VME: test planned with Type0 • Final boards • VirtexII or Spartan3 ? • MainFPGAXCV812E-8-FG900 is old, first production in 2000 • Connectors • Analog input by3M coaxialconnectors • LVDS connection by3M cables • Differential driver on the trigger board Type1 • Other components are fixed: FADC, LVDS Tx and Rx, Clock distributor • Ancillary boards: distribution of control signals • Design of final prototypes (Type1 and Type2) june 2004 • If tests are okstart of the mass production • Estimated production and test 1 year

  24. Jan 2002 Trigger 2002 2003 2004 2005 Prototype Board Final Prototype Full System now Design Manufactoring Assembly Test Milestone

  25. DRS2 Chip • DRS2 chip designed • 500 MHz – 5 GHz sampling speed • 8+2 channels, 1024 bins deep each • Readout speed up to 100 MHz (?) • Production • Submitted to UMC in Nov. 18th • 58 chips received in Jan. 15th • packaging 3 weeks • Tests planned Feb. ‘04 – April ‘04 • Redesign only if problems (next submission April or June ‘04) • Board integration – July ’04 (PSI GVME board) • Full chip production run in fall ‘04

  26. DRS2 Chip Layout Domino Circuit Readout shift register Die: 5 x 5 mm ~250,000 Transistors Chip: PLCC 68 2 Test channels 10 channels x 1024 bins

  27. PSI - Generic VME PMC carrier board

  28. PMC carrier board DRS 1st Prototype Joint effort with the MAGIC experiment (Uni. of Siena and INFN Pisa) • Clock control (locking to external source) • DRS readout with FADC • DRS control signals

  29. DRS (DAQ) 2002 2003 2004 2005 1st Prototype Tests 2nd Prototype Boards & Chip Test now Design Manufactoring Assembly Test Milestone

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