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CA Overview

CA Overview. Direct Mapped Cache. Accessing Direct-Mapped Cache. Set Associative Caches. Accessing Set Associative Caches. Actions on Write. Actions on Write. HW ILP. ILP. Dependency. Dependency. Dependency. Tomasulo Algorithm. Tomasulo Algorithm. Out-of-order Completion. ROB.

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CA Overview

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  1. CA Overview

  2. Direct Mapped Cache

  3. Accessing Direct-Mapped Cache

  4. Set Associative Caches

  5. Accessing Set Associative Caches

  6. Actions on Write

  7. Actions on Write

  8. HW ILP

  9. ILP

  10. Dependency

  11. Dependency

  12. Dependency

  13. Tomasulo Algorithm

  14. Tomasulo Algorithm

  15. Out-of-order Completion

  16. ROB

  17. ROB

  18. SW ILP

  19. Loop level Parallism

  20. Loop Unrolling

  21. Loop Unrolling

  22. VLIW

  23. VLIW

  24. Trace Scheduling

  25. Superblock

  26. Predicate Instruction

  27. Parallelism

  28. Parallelism

  29. Multiprocessor Systems • Continuous need for faster computers • shared memory model • message passing multiprocessor • wide area distributed system

  30. Multiprocessors • Definition:A computer system in which two or more CPUs share full access to a common RAM

  31. Bus-Based MP • Snooping cache protocols are employed • bus can be a bottleneck • limited scalability

  32. Interconnection NW: crossbar sw

  33. Multistage Interconnection NW • UMA multiprocessors using multistage switching networks can be built from 2x2 switches (a) 2x2 switch (b) Message format

  34. Omega Network

  35. Non-Uniform Memory Access NUMA Multiprocessor Characteristics • Access to remote memory slower than to local • Single memory space visible to all CPUs • Access to remote memory via commands • LOAD • STORE

  36. Cache Coherence Protocol • Depends on communication medium • bus-based snooping cache protocol • directory-based for MIN • Invalidation vs update • affected by lengths of write-run • cache line states usually denote • validity • write privilege • shared or private • modified (for write back)

  37. Cache Coherence Protocol

  38. Directory-Based MP (a) 256-node directory based multiprocessor (b) Fields of 32-bit memory address (c) Directory at node 36

  39. Multiprocessor OS Types (1) Each CPU has its own operating system Bus

  40. Multiprocessor OS Types (2) Master-Slave multiprocessors Bus

  41. Multiprocessor OS Types (3) • Symmetric Multiprocessors • SMP multiprocessor model Bus

  42. Multiprocessor Synchronization (1) • atomic TSL does not work • needs bus locking to prevent interrupts from other CPUs • busy wait with TSL may generate excessive bus traffic

  43. Massively Parallel Processor

  44. Massively Parallel Processor

  45. Massively Parallel Processor

  46. CMP Reminder

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