Short Channel Effects in MOSFETs

1. Short Channel Effects in MOSFETs Fabio D’Agostino Daniele Quercia Fall, 2000

2. Presentation Outline Short-Channel Devices Short-Channel Effects (SCE) The modification of the threshold voltage due to SCE A numerical example Simulation: SCE impacts on the threshold voltage Simualtion: limiting effect of the saturation velocity Conclusion

3. Definition • What is a “short-channel device”? • A MOSFET is considered to be short when the channel length is the same order of magnitude as the depletion-layer widths (xdD, xdS)

4. Short Channel Effects • Five different physical phenonomena have to be considered in short-channel devices: • Drain induced barrier lowering and Punchthrough • Surface scattering • Velocity saturation • Impact ionization • Hot electrons

5. Drain-induced barrier lowering (DIBL) • The electrons (carriers) in the channel face a potential barrier that blocks their flows • The potential barrier, in small-geometry MOSFETs, is controlled by a two-dimensional electric field vector (in other words by both VGS and VDS) • If the drain voltage is increased the potential barrier in the channel decreases, leading to Drain-Induced Barrier Lowering (DIBL)

6. Drain-induced barrier lowering (DIBL) and Punchthrough • Under DIBL condiction electrons can flow between the source and drain even if VGS < VT • The channel current that flows in this case is called subthreshold current Punchthrough • The DIBL phenomenon can be accompanied by the so-called punchthrough, that occurs when the depletion region surrounding the drain extends to the source • Punchthrough minimized with thinner oxide, larger substrate doping (and longer channel!)

7. Surface scattering For small-geometry MOSFETs, the electrons mobility in the channel depends on a two-dimensional electric field (x, y)

8. Surface scattering • The surface scattering occurs when electrons are accelerated toward the surface by the vertical component of the electric field x • The collision of the electrons causes a reduction in the mobility • Electrons moves with great difficult parallel to the interface • The average surface mobility is about half as much as that of the bulk mobility

9. Velocity saturation • For low ythe electron drift velocity vde in the channel varies linearly with the electric field intensity • Asyincreases above 104 V/cm the drift velocity tends to approach a saturation value of vde(sat)=107 cm/s around y=105 V/cm • The velocity saturation reduces the transconductance of short-channel devices in the saturation condiction, as the following formula shows: gm = W Cox vde(sat)

10. Impact ionization • The presence of high longitudinal fields can accelerate electrons that may be able of ionizing Si atoms by impacting against them • Normally most of the e- are attracted by the drain, so it is plausible a higher concentration of holes near the source • If the holes concentration on the source is able to creates a voltage drop on the source-substrate n-p junction of about 0.6V then • e- may be injected from source to substrate • e- travel toward the drain, increasing their energy and create new e-h pairs • e- may escape the drain fields and afect other devices

11. Hot electrons The channel Hot Electrons effect is caused by electrons flowing in the channel for large VDS e- arriving at the Si-SiO2 interface with enough kinetic energy to surmount the surface potential barrier are injected into the oxide This may degrade permanently the C-V characteristics of a MOSFETs

12. The modification of the threshold voltage due to short-channel effects

13. Modification of VTH due to SCE • Equation giving the threshold voltage at zero-bias • accurate for large MOS transistors • not accurate for short-channel MOS transistors • the amount of bulk charge is overestimated

14. Modification of VTH due to SCE • Large MOS transistor: the deplition is only due to the electric field created by the gate voltage. • Small-geometry transistor: in addition to the previous contribution, the deplition charge near n+ regions is induced by p-n junctions.

15. Modification of VTH due to SCE

16. DVT0: threshold voltage shift • VT0: zero-bias threshold voltage Modification of VTH due to SCE • The bulk depletion charge is smaller than expected • the threshold voltage expression must be modified to account for this reduction:

17. Modification of VTH due to SCE • We find the following relationship:

18. … and solving for D LDwe obtain : where • Similarly, the length D LScan also be found as follows: where Modification of VTH due to SCE

19. Modification of VTH due to SCE • The amount of the threshold voltage reduction • D VT0 due to short-channel effects can be found as:

20. Modification of VTH due to SCE • Numerical example • We consider an n-channel MOS process with the following parameters: • substrate doping density NA=1016 cm-3, • polysilicon gate doping density ND (gate) = 2 1020 cm-3, • gate oxide tickness tox= 50 nm, • oxide-interface fixed charge density Nox=4*1010cm-2 , • source and drain diffusion doping density ND= 1017 cm-3. • In addition, we assume that the channel region is implanted with p-type impurities • (impurity concentration NI= 2 1011 cm-2) • Moreover, the junction depth of the source and drain diffusion regions is xj=1.0 mm.

21. Modification of VTH due to SCE • We obtain … VT0= 0.855V - D VT0; where ___________ DVT0= ( 0.343/ L[mm] ) * (-0.724 +  ( 1 + 2 xdD) _________________ xDd=  0.13 (0.76 + VDS)

22. Modification of VTH due to SCE • … and plotting the variation of the threshold voltage with the channel lenght

23. Simulation: impact of SCE on the threshold voltage We simulate four nMOSFETs in parallel, with different channel lengths and widths All the transistors have the same parameters; LEVEL 2 of Pspice is used For each transistor we generate the ID-VGS characteristic at VDS = 0.1V The plots show how devices with smaller geometry have higher drain currents at the same gate-to-source voltage (i.e., smaller threshold voltages)

24. Simulation: impact of SCE on the threshold voltage

25. Simulation: the limiting effects of the saturation velocity We simulate two nMOSFETs in parallel, with the same channel length and width One transistor has a limited saturation velocity of vde(sat) = 2·106 cm/s; LEVEL 2 of Pspice is used For each transistor we generate the ID-VDS characteristic at VGS = 5V The plots show the reduction of the transcoductance in the saturation mode

26. Simulation: the limiting effects of the saturation velocity

27. Conclusion • SCE are governed by complex physical phenomena that can be mainly related to the Influence of both vertical and horizontal electric field components on the flow of the electrons in the channel • Usually SCE interacts the one with the other • SCE should be carefully considered in order to evaluate their impact on the general behaviour of the device, both for short-term and long-term