1 / 39

Effects of Parasitic Components in High-Frequency Resonant Drivers for Synchronous Rectification MOSFETs

Effects of Parasitic Components in High-Frequency Resonant Drivers for Synchronous Rectification MOSFETs . Speaker: Giorgio Spiazzi. Department of Information Engineering – DEI University of Padova, ITALY. Outline. Review of voltage source driver topology

posy
Download Presentation

Effects of Parasitic Components in High-Frequency Resonant Drivers for Synchronous Rectification MOSFETs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Effects of Parasitic Components in High-Frequency Resonant Drivers for Synchronous Rectification MOSFETs Speaker:Giorgio Spiazzi Department of Information Engineering – DEI University of Padova, ITALY

  2. Outline • Review of voltage source driver topology • Analysis of resonant voltage source driver topologies • Unclamped turn-on and clamped turn-off • Clamped turn-on and clamped turn-off • Unclamped turn-on and unclamped turn-off • Analysis of parasitic component effects

  3. +Vdd S1 Rch M S2 Voltage Source Topology Dissipative driver Ron i(t) + + Vgon C vC(t) Ron = RDSon(S1)+Rch+Rg

  4. S1 Lext M Db1 + Vdd Db2 Dc1 S2 + Vo Resonant Driver DR1 Unclamped turn-on and clamped turn-off Possible energy recovery to output in VRM applications

  5. Resonant Driver DR1 VCon Ipk_p vC(t) i(t) Toff VCoff t tri tfu Ton ig(t) I1 Ipk_n Unclamped turn-on and clamped turn-off S1 Lext M Db1 + Vdd + i(t) Db2 vC Dc1 S2 + Vo -

  6. Resonant Driver DR1 VCon Ipk_p vC(t) i(t) Toff VCoff t tri tfu Ton ig(t) I1 Ipk_n Turn-on phase VDb RDSon Lint RLp Lext Rg + S1 + M Db1 Vdd C Ron L Resonant circuit parameters + i(t) + vC(t) Vgon C

  7. Resonant Driver DR1 Inductor current and capacitor voltage If Qon>>1: Final capacitor voltage

  8. Unclamped Resonance Normalized capacitor voltage and inductor current as a function of wot for different Q values (vC(0) = 0, VN = Vgon, IN = Vgon/Zo) Q = 1000 Ton 2 1 Q = 10 [IN] [VN] Q = 5 1.6 0.8 Q = 2 Q = 1 1.2 0.6 Q = 0.5 0.8 0.4 0.4 0.2 0 0 0

  9. 2 1 [h] [VN] 1.8 0.8 1.6 0.6 Normalized final capacitor voltage 1.4 0.4 1.2 0.2 1 0 0.1 1 10 100 Q Unclamped Resonance Ideal performance comparison between a voltage source and an unclamped resonant drivers 0.5

  10. UnclampedResonance • High Q means high L, that means lower resonant frequency, i.e. higher turn on interval • Minimum loss resistance is the SR gate internal resistance Rg For a voltage source topology:

  11. Maximum Ron a = 0.05, k = 0.8, Ron_min = 1W, C = 10nF Ron [W] 100 Voltage source topology 10 Q = 0.5 Ron_min Q = 1 1 Unclamped resonance topology Q = 2 Q = 4 0.1 fsw [MHz] 0.01 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

  12. Resonant Driver DR1 VCon Ipk_p vC(t) i(t) Toff VCoff t tri tfu Ton ig(t) I1 Ipk_n Turn-off phase Roff L + i(t) + vC(t) Vgoff C Roff-Rg Rg L ig(t) + i(t) + Vgoff vC(t) C VDc +

  13. DR1 Characteristics • both switches S1 and S2 turn on and off at zero current; • the control signals of S1 and S2 have no critical timing, the only requirement being to avoid any cross conduction; • the switching times of S1 and S2 have no influence in the circuit behavior; • S1 and S2 body diodes are not used (they have high voltage drop and bad reverse recovery behavior); • switch lead inductances as well as any parasitic inductance due to traces and layout simply add to the external inductance (they are actually exploited by the circuit); • different Ton and Toff times can be easily achieved; • Toff interval duration as well as the amount of recovered energy depends on Vo value (disadvantage); • S2 command signal must be suitably higher than Vo to completely turn it on (disadvantage). • No low impedance paths during on and off intervals

  14. Ipk_p I2 I3 VCon i(t) vC(t) ig(t) Toff VCoff t tfi tfw tri tfw tru tfu Ton Ipk_n Resonant Driver DR2 Clamped turn-on and clamped turn-off Dc1 and Dc2 can be substituted by MOSFETs, thus ensuring a low impedance path to Vdd an to ground during on-time and off-time +Vdd Dc2 S1 Lext M S2 Dc1

  15. Ipk_p I2 I3 VCon i(t) vC(t) ig(t) Toff VCoff t tfi tfw tri tfw tru tfu Ton Ipk_n Resonant Driver DR2 Turn-on phase VDc + Ron-Rg Rg L + Vdd ig(t) i(t) + C vC(t) Ron L VDc + + i(t) Rg RLp + L + vC(t) Vgon Vdd C ig(t) i(t) + VD2 C vC(t) +

  16. DR2 Characteristics • both S1 and S2 switches turn on at zero current, but they turn off almost at the inductor peak current; • the control signals of S1 and S2 have critical timing, having to minimize the freewheeling intervals tfw, in order not to adversely affect the overall efficiency; • the switching times of S1 and S2 have a great influence on the circuit behavior, causing a significant power loss at turn off (see point 1) as well as increase of Ton and Toff intervals; • S1 and S2 body diodes are involved during the recovery of the inductor energy; • switch lead inductances as well as any parasitic inductance due to traces and layout have a great impact on the circuit behavior, since they cause high frequency parasitic oscillations at turn off and delay S1 and S2 turn off times; • VCon value is easily controlled by the supply voltage Vdd (advantage)

  17. VCon Ipk_p +Vdd vC(t) i(t) Toff S1 t M Db1 Ton Lext VCoff Db2 Ipk_n S2 Resonant Driver DR3 Unclamped turn-on and unclamped turn-off

  18. DR3 Characteristics Same considerations as DR1. Moreover: • high VCon values can be achieved with very low supply voltage Vdd; • Vdd value must be higher than the threshold voltage of S1 (p-channel MOSFET) in order to fully turn it on; • the driver needs some oscillating cycles in order to achieve a steady state operation

  19. Losses Comparison Driver parameters: • S1,2 = IRF7319 • Db1,2, Dcl, and Dc1,2 = STPS1L40U • Switching frequency: fsw = 1.8MHz • Maximum diode voltage drop: VDc = VDb = 0.63V • External inductance parasitic resistance: RLp = 200mW • External inductance: Lext = 30nH (DR1), Lext = 35nH (DR2), Lext = 30nH (DR3) • Internal gate resistance: Rg = 0.25W • Equivalent gate capacitance: C = 10nF • Supply voltage: Vdd = 5V (DR1), Vdd = 6.8V (DR2), Vdd = 3.85V (DR3) • VRM output voltage for DR1: Vo = 1.3V

  20. Losses Comparison: calculations MOSFET S1 and S2 parameters Details of Losses Calculation for DR1 (VCon = 7.41V, Lext = 30nH, Vdd = 5V, Vo = 1.3V)

  21. Losses Comparison Details of Losses Calculation for DR2 (VCon = 7.43V, Lext = 35nH, Vdd = 6.8V) Details of Losses Calculation for DR3 (VCon = 7.44V, VCoff = -3.71V,Lext = 30nH, Vdd = 3.85V)

  22. Losses Comparison Driver DR2 losses do not include S1 and S2 switching losses: at turn-on: Psw_on = 220mW at turn-off: Psw_off = 135mW Total DR1 losses: Ptot_loss = 502mW Total DR2 losses: Ptot_loss = 574+355 = 929mW Total DR3 losses: Ptot_loss = 773mW

  23. vC[2V/div] vRs[100mV/div] vG_p-MOS[1V/div] VGS_n-MOS[1V/div] vDS_n-MOS [2V/div] Experimental Waveforms: DR1 With Lext CLoad = 10nF (smd), Rs = 0.1W, Ualim = 5V, fsw = 1.8MHz + Dcl1 VC C Rs + VRs

  24. vC[2V/div] vRs[200mV/div] vG_p-MOS[1V/div] VGS_n-MOS[1V/div] vDS_n-MOS [2V/div] Experimental Waveforms: DR1 Without Lext CLoad = 10nF (smd), Rs = 0.1W, Ualim = 5V, fsw = 1.8MHz + Dcl1 VC C Rs + VRs

  25. vC[2V/div] vRs[100mV/div] vG_p-MOS[2V/div] VGS_n-MOS[2V/div] vDS_n-MOS [2V/div] Experimental Waveforms: DR2 Non zero capacitor voltage during off interval With Lext Final capacitor voltage lower than expected CLoad = 10nF (smd), Rs = 0.1W, Ualim = 7.5V, fsw = 1.8MHz TpNMOS = 58.4ns, TpPMOS = 58.4ns (misurati a 1V)

  26. vC[2V/div] vRs[200mV/div] vG_p-MOS[2V/div] VGS_n-MOS[2V/div] vDS_n-MOS [2V/div] Experimental Waveforms: DR2 Without Lext CLoad = 10nF (smd), Rs = 0.1W, Ualim = 7.5V, fsw = 1.8MHz TpNMOS = 58.4ns, TpPMOS = 58.4ns (misurati a 1V)

  27. vC[2V/div] vRs[100mV/div] vG_p-MOS[1V/div] VGS_n-MOS[1V/div] vDS_n-MOS [2V/div] Experimental Waveforms: DR3 With Lext Negative capacitor voltage during off interval CLoad = 10nF (smd), Rs = 0.1W, Ualim = 4V, fsw = 1.8MHz

  28. vC[2V/div] vRs[200mV/div] vG_p-MOS[1V/div] VGS_n-MOS[1V/div] vDS_n-MOS [2V/div] Experimental Waveforms: DR3 Without Lext CLoad = 10nF (smd), Rs = 0.1W, Ualim = 4V, fsw = 1.8MHz

  29. [V,A] vDS_n-MOS 8 VCon 6 4 vC 2 iL 0 VCoff -2 Time -4 Effect of Device Parasitic Capacitances The final capacitor voltage during turn on is lower than expected, especially for driver DR2. Why? RLp Lext + Vdd Effect of device’s output capacitances i(t) + + Cp C vCp vC [V,A] vDS_n-MOS 8 VCon_nominal 6 VCon 4 vC 2 iL VCoff 0 -2 Ton_sw = 90ns Ton_sw = 150ns Time -4 X axis scale = 50ns/div

  30. Effect of Device Parasitic Capacitances DR2 Measurements: Vdd = 7V, fsw = 1.8MHz, Lext= 0 vc(t) [2V/div] Tsw-cond = 90ns Tsw-cond = 60ns Time [100ns/div]

  31. Effect of Device Parasitic Capacitances DR2: Effect of Switch Conduction Time on VCon and VCoff (Vdd = 7V, Rs = 0)

  32. DR1 Power Losses at Different Vdd (Rs = 0, Vo = 0)

  33. DR2 Power Losses at Different Vdd (Rs = 0, Tsw-cond = 58.4ns)

  34. DR3 Power Losses at Different Vdd (Rs = 0)

  35. Internal MOSFET Inductance • For the same Vdd value, the final VCon voltage without the external inductor Lext in DR1 and DR3 (and, to a less extent, also in DR2) is much lower than the corresponding value with Lext, and this phenomenon is more pronounced at lower Vdd values • This result can be explained only by a lower Qon factor of the circuit without Lext, i.e. a higher RDSonof the p-channel MOSFET S1 caused by a reduced gate-to-source voltage due to the voltage drop across the internal source inductance (4nH for the IRF7319) that becomes worse at higher di/dt values, i.e. without Lext. This explains why the observed phenomenon is more pronounced at lower Vdd values, and justify why DR1, that requires a higher Vdd than DR3 to achieve the same VCon value, has lower overall losses than DR3 even without energy recovery.

  36. Resonant VRM VGS_Q1 Q1 C1 CA VC1 + LF1 iF1 HB1 LR CF TR + + VO VIN iR RL iF2 HB2 LF2 VC2 N:1 + CB C2 Q2 VGS_Q2 • Square-wave operation of the primary half-bridge • Zero-voltage and zero-current commutations of SR MOSFETs Q1 and Q2 • Operation at fs = 1.8MHz, VIN = 48V, Vo = 1.3V, Io = 50A • Resonant drivers for SRs

  37. VRM Prototype 4 IRF7836 SR MOSFETs (Qg = 18-27nC @VGS = 4.5V, Rg = 1W)

  38. VGS1 [2V/div] VGS2 [2V/div] Experimental Waveforms: DR1 DR1 measured waveforms driving 4 IRF7836 SR MOSFETs (no energy recovery) Ploss = 1W each HB1 HB2

  39. References • D. Maksimovic, “A MOS gate drive with resonant transitions,” in Proc. Power Electron. Spec. Conf., 1991, pp. 527–532. • Y. Ren, M. Xu, Y. Meng, F. C. Lee, “12V VR Efficiency Improvement based on Two-stage Approach and a Novel Gate Driver,” IEEE Power Electronics Specialists Conf. (PESC), June 2003, pp.2635-2641. • T. Lopez, G. Sauerlaender, T. Duerbaum, T. Tolle, “A Detailed Analysis of a Resonant Gate Driver for PWM Applications,“ IEEE Applied Power Electronics Conf. (APEC), 2003, pp. 873-878. • K. Xu, Y. F. Liu and P. C. Sen, “A New Resonant Gate Drive Circuit with Centre-Tapped Transformer,” IECON, 2005, pp. 639-644. • Z. Yang, S. Ye and Y. F. Liu, “A New Dual Channel Resonant Gate Drive Circuit for Synchronous Rectifiers,” IEEE Applied Power Electronics Conf. (APEC), 2006, pp. 756-762. • Z. Zhang, Z. Yang, S. Ye, Y. F. Liu, “Topology and Analysis of a New Resonant Gate Driver,” IEEE Power Electronics Specialists Conf. (PESC), June 2006, pp. 1453-1459. • W. A. Tabisz, P. Gradzki, and F. C. Lee, “Zero-voltage-switched quasi-resonant buck and flyback converters—experimental results at 10 MHz,”IEEE Power Electronics Specialists Conf. (PESC), 1987, pp. 404–413. • S. H. Weinberg, “A novel lossless resonant MOSFET driver,” IEEE Power Electronics Specialist Conf. (PESC), 1992, pp. 1003–1010. • H. L. N. Wiegman, “A resonant pulse gate drive for high frequency applications,” IEEE Applied Power Electronics Conf. (APEC), 1992, pp. 738–743. • Y. Panov and M. Jovanovic, “Design considerations for 12-V/1.5-V, 50-A voltage regulator modules,” IEEE Transactions. on Power Electronics, Vol.16, N°6, Nov. 2001, pp. 776-783. • Y. Chen, F. C. Lee, L. Amoroso, H. P. Wu, “A resonant MOSFET Gate Driver with Efficient Energy Recovery,” IEEE Transactions on Power Electronics, Vol. 19, NO. 2, March 2004, pp.470-477. • S. Pan, P. K. Jain, “A New Pulse Resonant MOSFET Gate Driver with Efficient Energy Recovery,” IEEE Power Electronics Specialists Conf. (PESC), June 2006. • W. Eberle, P. C. Sen and Y. F. Liu, “A New Resonant Gate Drive Circuit with Efficient Energy Recovery and Low Conduction Loss,” IECON, 2005, pp. 650-655. • W. Eberle, Y. F. Liu and P. C. Sen, “A novel High Performance Resonant Gate Drive Circuit with Low Circulating Current,“ IEEE Applied Power Electronics Conf. (APEC), 2006, pp.324-330. • K.Yao, F. C. Lee, “A Novel Resonant Gate Driver for High Frequency Synchronous Buck Converters,” IEEE Transactions on Power Electronics, Vol. 17, No. 2, March 2002, pp. 180-186. • I. D. de Vries, “A resonant power MOSFET/IGBT gate driver,”IEEE Applied Power Electronics Conf. (APEC), 2002, pp. 179–185. • J. T. Strydom, M. A. de Rooij, J. D. van Wyk, “A Comparison of Fundamental Gate-Driver Topologies for High Frequency Applications,” IEEE Applied Power Electronics Conf. (APEC), 2004. • L. Huber, K. Hsu, M. Jovanovic, “ 1.8 MHz, 48 V Resonant VRM,” IEEE Tran. on Power Electronics, Vol.1, N°1, Jan. 2006, pp. 79-88.

More Related