Memory and I/O subsystem

1. Memory and I/O subsystem Reference: Introduction to Digital System by Ercegovac, Lang & Moreno, Wiley Publisher

2. Basic components of a computer • PROCESSOR; • MEMORY SUBSYSTEM; • INPUT/OUTPUT (I/O) SUBSYSTEM

3. Memory hierarchy

4. Specification of a simple processor System

5. Memory Subsystem

6. Entity Declaration of memory Subsystem LIBRARY ieee; USE ieee.std_logic_1164.all; USE WORK.comp_pkg.ALL; ENTITY Memory IS PORT (Addr : IN MAddrT ; -- memory address bus Length : IN STD_LOGIC; -- byte/word operand Rd, Wr : IN STD_LOGIC; -- access control signals Enable : IN STD_LOGIC; -- enable signal Rdy : OUT STD_LOGIC; -- access completion signal Data : INOUT WordT ); -- memory data bus END Memory;

7. I/O subsystem

8. Entity Declaration of I/O subsystem LIBRARY ieee; USE ieee.std_logic_1164.all; USE WORK.comp_pkg.ALL; ENTITY IO IS PORT (Addr : IN IOAddrT ; -- I/O address bus Length : IN STD_LOGIC; -- byte/word control Rd, Wr : IN STD_LOGIC; -- I/O access control Enable : IN STD_LOGIC; -- I/O enable control Rdy : OUT STD_LOGIC; -- I/O completion signal Data : INOUT WordT ); -- I/O data bus END IO;

9. PROCESSOR • Processor state • 32 general-purpose registers (32-bits wide), called R0, R1, ..., R31; • a 24-bit Program Counter register (PC); • a 4-bit Condition Register (CR); and • a 32-bit Instruction Register (IR).

10. Processor State

11. Behavior of Processor

12. Behavior of Instruction

13. INSTRUCTION SEQUENCING • SEQUENTIAL UNLESS • 1. UNCONDITIONAL BRANCH • 2. CONDITIONAL BRANCH

14. Instruction Format

15. Instruction Set

16. Instruction set (cont.)

17. Instruction set (cont.)