50 likes | 144 Views
REU Schedule Update. August 13: Graduate Fellowship Seminar Steven Conolly 10 AM Packard 101 August 13: Early Departure Poster Session: -Nemil Dalal, Chen Tze Wee, Steven Pu, Alan Amaya, Jianbo Wang, Shijun Liu, Jinendra Jain, Ravi Sarin August 20: Blaine Chronik, PhD
E N D
REU Schedule Update • August 13: Graduate Fellowship Seminar • Steven Conolly 10 AM Packard 101 • August 13: Early Departure Poster Session: -Nemil Dalal, Chen Tze Wee, Steven Pu, Alan Amaya, Jianbo Wang, Shijun Liu, Jinendra Jain, Ravi Sarin • August 20: Blaine Chronik, PhD • August 27: REU posters (about 3 pm) • End of Program August 30th • $1,150 final payment
Poster General Information • Size: 3 feet by 4 feet • Corkboard easels will be provided on August 27 • Format: Powerpoint slides or full poster • Legible: 66 point for titles, authors; 36 point readable text font, 24 point captions • Background, goals, methods, results, discussion, conclusion • Stand by poster and explain it to people • Atmosphere of engineering research conference • Feel free to bring circuit to show
REU Contact Information • REU Program Coordinator • Susan Farrell, Packard 172 sfarrell@stanford.edu 6-2070 • Research Advisor • Steven Conolly, PhD. Packard 206 sc@quench.stanford.edu • If you cannot attend August 27 poster presentation see me after presentation today.
Professor Robert Dutton • Robert and Barbara Kleist Professor of Electrical Engineering • Director of Research in the CIS. • Teaches EE 111, 113, 133 Analog Electronics • Degrees from UC Berkeley • Worked at Fairchild, Bell Labs, HP, IBM, and Matsushita • Research focus on IC CAD and parallel computational methods. • More than 200 journal articles and graduated more than four dozen doctorate students.
Professor Robert Dutton • Awards: 1987 IEEE J. J. Ebers Award, 1988 Guggenheim Fellowship; National Academy of Engineering 1991; Jack A. Morton Award and the C & C Prize, 2000 • Developed industry-standard modeling code SUPREM and PISCES. • Co-founder of Technology Modeling Associates (TMA), now part of Avant! • “Device Modeling and Simulationfor VLSI Design”