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Microprocessor system architectures – IA32 tasks

Microprocessor system architectures – IA32 tasks. Jakub Yaghob. Using tasks in OS. 1 thread = 1 task 1 process = 1 task All processes = 1 task. Structure of a task. Task state. Segment selectors CS , DS , ES , FS , GS , SS General registers EAX - ESP Flags EFLAGS

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Microprocessor system architectures – IA32 tasks

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  1. Microprocessor system architectures – IA32 tasks Jakub Yaghob

  2. Using tasks in OS • 1 thread = 1 task • 1 process = 1 task • All processes = 1 task

  3. Structure of a task

  4. Task state • Segment selectorsCS, DS, ES, FS, GS, SS • General registersEAX-ESP • FlagsEFLAGS • Instruction pointerEIP • Control registerCR3 • Private paging virtual address space • The state ofTR • Selector inLDTR • The I/O map • Software interrupt redirection map (Pentium+) • Stack pointers to the 0-2 privilege level stacks • Link to previously executed task

  5. Involved registers and data structures • Task State Segment • TSS • TSS descriptor • Task gate descriptor • Task registerTR • The flagNTinEFLAGS • NT = Nested Task

  6. TSS structure

  7. Fields in the TSS 32b– I

  8. Fields in the TSS 32b– II

  9. Fields in the TSS 32b– III

  10. TSS descriptor 32b

  11. Task gate descriptor

  12. Using task gate

  13. Task register • Holds a selector to a TSS descriptor • Hidden part • Current task

  14. Task switching • Explicit switch • Explicit task switching as a subprogram usingCALL • Explicit task switching using JMP • As a target is either TSS descriptor or task gate descriptor • Checking EPL ≤ DPL • Implicit switch • Implicit switch (CPU makes it during some operation) for interrupt or exception handling • A target task is providedby task gate descriptor in the IDT • Return from a task using IRETwith pre-setNTinEFLAGS • Return from „subprogram“ • A target task taken from the LINK field of the current TSS

  15. Obtaining a target TSS Checking EPL ≤ DPL The target task is present and its length≥67h The target task is available for jumps or busy for return Paging in current, target TSSs and all used descriptors Clearing B in the old descriptor for JMP and IRET, leaving original B (=1) for CALL and IRQ Clearing NT executing IRET Storingcurrent state into current TSS Setting NT in new EFLAGSexecuting CALL or during IRQ, keeping the NT value from new EFLAGS executing JMP or IRET Setting B in the new descriptor for JMP, CALL, IRQ, leaving original B for IRET Loading TR with new TSS descriptor Loading a new state from TSS Loading new segment descriptors Executing the new task Task switching – mechanism

  16. Task linking • Only whena task is switched using CALL or an interrupt/exception handling using a task gate • It is not possible to make a recursion

  17. Task management in long mode • Task switching not available • All attempts cause #GP • 64-bit TSS must exist • RSPn – stacks for privilege levels 0-2 • ISTn – Interrupt Stack Table • I/O map

  18. Fields in the TSS 64b– I

  19. Fields in the TSS 64b– II

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