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LBNL: 65nm pixel activities

LBNL: 65nm pixel activities. ATLAS-CMS 65nm Pixel ASIC Meeting Dario Gnani for DICES Group (*) November 26-27, 2012 (*) Abderrezak Mekkaoui, Brad Krieger, Jean-Pierre Walder , Carl Grace, Bob Zheng 1 , Henrik von der Lippe , Peter Denes, Devis Contarato ,…. 1: now at Rice University.

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LBNL: 65nm pixel activities

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  1. LBNL: 65nm pixel activities ATLAS-CMS 65nm Pixel ASIC Meeting Dario Gnanifor DICES Group (*) November 26-27, 2012 (*) Abderrezak Mekkaoui, Brad Krieger, Jean-Pierre Walder, Carl Grace, Bob Zheng1, Henrik von der Lippe, Peter Denes, DevisContarato,… 1: now at Rice University

  2. Talk Summary • 65nm Pixel Readout ASICs for HEP • FE-I5-P1: prototype of next-generation hybrid pixel readout ASIC • Non-HEP 65nm Pixel ASICs • HipPix400: prototype of MAPS ASIC for Electron Microscopy (EM) • Other 65nm ASICs • DCDC65nm: prototype of 4-to-1 DC-DC converter • HIPPO: prototype for new high-speed CCD readout ASIC • POM: prototype for a multi-channel straw readout ASIC for FermiLab Mu2e experiment

  3. 65nm adoption background • Benefit from trend in manufacturing costs to skip a CMOS generation • Longer availability allows for • IP re-use in different designs • Absorb tech transition overhead over longer lifespan • Need of better efficiency for similar performance in future projects (fTgm/Id scaling) • Reduced costs at time of full engineering runs

  4. LBNL 65nm strategy • Consolidate several projects into a single MPW run (chiplets) • Move to new design topologies with larger role for digital design • Develop/acquire new engineering skills in 65nm and mixed-mode designs • Build part and IP libraries • Develop verification and digital P&R flows (e.g. analog functional verification) • Select foundry by tech performance and run availability • Develop prototypes using “tiny” chip runs

  5. FE-I5-P1: Background 1/2 • Explore capabilities of advanced CMOS processes to address future HEP needs (Upgrades, High Luminosity LHC) • Establish an analog front-end baseline • Learn the best way these processes should be used in order to maximize benefit • Evaluate radiation hardness A. Mekkaoui - TWEPP 2012

  6. FE-I4 : Front End chip for the IBL FE-I5-P1: Background 2/2 • The FE-I4B chip is the production version for IBL installation • Process: 130nm CMOS twin-well process • Dimensions: 20mm x 19mm (full-reticle) • Active area: ~90% of the total area • Respects all the specifications • IBL Production : 1 Module =1 Chip • The FE-I4 pixel array is organized in Double Columns (DC) • Double Column is divided into 2×2 pixel Regions • 1 Region: 2×2 pixel • Pixel size: 50x250 µm² • Array size: 336x80=26880 pixels • Radiation tolerance: > 200Mrad • Phase I or Phase II • New pixel detector planned • 2 removable inner layers at radii of 3.3–10cm • 2-3 fixed outer layers at radii of about 15–25cm • FE-I4 fits requirements for outer layers in terms of hit occupancy and radiation hardness • A new development (FE-I5) is required for the inner layers • 20.2 mm • 336×80 pixel array • 16.8 mm • 2 mm • IO pads • Periphery • Main functional core A. Mekkaoui - TWEPP 2012

  7. FIE4 pixel region Vs Pix65nm region (assuming y=50u) FE-I5-P1: Description 1/4 FEI4 2X2 REGION (100X500) “FEI5” 2X2 REGION (100X200) If area to be kept the same as FEI4, about 4X more logic can be added • Substantial area reduction • Ultimately the width of a pixel will limited by practical considerations (power distribution) and not the number of transistors! • Room to add functionality • Need to explore new analog front-ends to keep up with digital scaling A. Mekkaoui - TWEPP 2012 7

  8. FE-I5-P1: Description 2/4 Passive RC: gate leakage limited TDAC (+/- 4b tuning) Preamp: 17fF Feedback cap. Variable “Rff” Inject Block Single to differential + Comparator “preamp” Comparator • Uses only thin-oxide 65nm Transistors • 2mA to 25mA @ 1.2V A. Mekkaoui - TWEPP 2012

  9. FE-I5-P1: Description 3/4 Config. Logic Config. Logic Analog FE Future Digital Region nXm pixels Analog FE Bump opening FE-I4 PIXEL SIZE • Region above same size as 2x1 FE-I4 pixels • 25mm cell y-pitch w/ 50mm bump y-pitch • Power distribution major factor in x-pitch scaling (125mm in FE-I5 ) • Bump mask not part of the submitted layout (same bump size as FEI4) • Test new std-cell-based SEU-tolerant latch A. Mekkaoui - TWEPP 2012

  10. FE-I5-P1: Description 4/4 • 2.6 mm 16 X 32 array 25m X 125m pixels Pixels with added mim-caps (31,27,22,18) A. Mekkaoui - TWEPP 2012 Pixels with added sensors (row 11:31) • 1.8 mm

  11. FE-I5-P1: Results 1/3 Chan 15/32 Qin: 2 to 10ke- Qin=10ke-; 5 IFF settings A. Mekkaoui - TWEPP 2012

  12. FE-I5-P1: Results 2/3 s> than FEI4 (as expected!) Channels with caps or diodes Sigma(untuned) ~350e- rms Sigma(tuned) < 60e- rms A. Mekkaoui - TWEPP 2012 ---- 565e- p-p tuned ----

  13. FE-I5-P1: Results 3/3 Radiation Effects Errors plot for the configuration cell (TRL) All patterns Pattern 0000 Pattern 1111 A. Mekkaoui - TWEPP 2012 M. Menouni- TWEPP 2012 Rows 0-255 • VG of diode-connected FETs at fixed current • Different size transistors • Small/negligible change in threshold voltages of PFETs/NFETs • PFET threshold variation more pronounced! • Some measurement errors in low current regime (meter impedance and ESD diode leakage) • New std cell based SEU tolerant latch + register • triple-redundant • self-correcting • read-back • ROM default • Similar performance to FE-I4 latch • 2-3x10-16 cm2/bit Columns 0-15 Columns 0-15 Columns 0-15

  14. HipPix400: Background/Descr./Results • CMOS detectors offer major advantages over CCD cameras in TEM applications: • Improved PSF • Lower dose • Higher speed 0.18 um CMOS K2 sensor (2010) 5m pixels • 16Mpix, 400 f/s Improved radiation tolerance Commercialproduct B.Krieger, TNS 2012; Commercial partner

  15. HipPix400: Background/Descr./Results 0.18 um CMOS K2 sensor (2010) 5m pixels • 16Mpix, 400 f/s Improved radiation tolerance Commercial product 0.35 um CMOS • TEAM2k(2009) • 9.5m pixels 4Mpix, 400 f/s HIPPIX (2011) 65nm proto • 0.35 um CMOS(2009) TEAM1k 1 Mpix B.Krieger, TNS 2012

  16. HIPPO: Background column-Parallel LBNL CCD Custom 65nm CMOS 35 e- @ 10 Mpix/s • Megapixel square sensor has ~1000 columns @ 50 μm pitch  need custom IC readout • No room for output amplifier need charge-sensitive readout • Ultimate applications require intensive DSP  advanced CMOS process • 65nm CMOS found to be the most adequate C. Grace, TNS 2012

  17. HIPPO: Description 1/2 4200 μm 16 Analog Front ends SERDES (480 Mb/s) 16 SHAs 4 ADCs 12b (80 Msps) Thick-ox input transistor to achieve the required noise level. Nominal transistor is too leaky!

  18. HIPPO: Description 2/2 Preamp J.P. Walder, TNS 2012 ADC

  19. POM: Background • SPECIFICATIONS (FNAL mu2e experiment) • Straw interface: • dissipative transmission line (300 Ohm) • 100ns tail • e- vs p+ discrimination • ADC 8-bit, 16ns samples • Positioning => timing resolution 50ps diff • TDC specs • FE noise specs • Low power: ~10mW/chan • Synchronous inhibit, low occupancy • Radiation tolerance • Two Possible Readout Electronics Schemes: • FNAL • Discrete preamp • Analog signal distribution • LBNL • Integrated preamp • Digital communication • ASIC can work in both configurations

  20. POM: Description/Results chip B chip A • Each channel performs the following functions on each end of the straw: • Front-end (5mW) • FE matching (75 to 300 Ohm) • Low-noise current-to-voltage conversion (3fC for 100fC - min input signal) • Adjustable pole-zero cancellation (60ns base-base) • Discrimination (σt~30ps) • Time stamping (16-bit, 35ps, 1.5mW dual-channel TDC) • Only one end: • Single-to-diff conversion • Amplitude sampling (8-bit, 16ns, 4mW, pipeline ADC) • Digital buffering and serialization (65Mbps) q

  21. POM: Results

  22. DCDC-65nm • General purpose test vehicle • Topologies that offer straightforward gate drive, LV blocking voltage • Able to test internal and external cap operating modes • Non-optimal due to limited die area available on this project • 4:1, 10’s MHz, 100mW/mm 2 • Clkin/Clk out supports interleaved operating mode with mutiplechips • Missing masks in first run… Brad Krieger - ATLAS upgrade 2012

  23. Lessons Learned • Interface IPs • gain experience with small pitch wire-bonding • use staggered pads • use circuit-under-pad layouts • MS/RF compatible with LO libraries • large overhead for initial customization of free resources • Logic IPs • require customization for substrate isolation • unclear total dose performance • Flows • expect out-of-date tech-files for P&R rules • very strong impact of second order effect: tune RC extraction • rgateMod parameter in BSIM4 for schematic-level noise estimates • Foundry • Use “tiny” chip process stack for all designs • Specify the expected stack and options as “special handling”in submission forms even if redundant (esp. RDL)

  24. LBNL 65nm References • FE-I5-P1 • TWEPP 2012 • HSTD-8 • HipPix400 • TNS 2012 • IEEE 2012 - Anaheim • HIPPO • TIPP 2011 • NSS 2011 - Valencia • TNS 2012 • POM • IEEE 2012 - Anaheim • DCDC-65nm • ATLAS Upgrade 2012 - Stanford

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