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Single Event Upset and Hardening in 0.15µm Antifuse-Based FPGA

Single Event Upset and Hardening in 0.15µm Antifuse-Based FPGA. J.J. Wang 1 , W. Wong 1 , S. Wolday 1 , B. Cronquist 1 , J. McCollum 1 , R. Katz 2 , and I. Kleyner 3 1 Actel Corporation, Sunnyvale, CA94086 2 NASA Goddard Space Flight Center, Greenbelt, MD20771

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Single Event Upset and Hardening in 0.15µm Antifuse-Based FPGA

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  1. Single Event Upset and Hardening in 0.15µm Antifuse-Based FPGA J.J. Wang1, W. Wong1, S. Wolday1, B. Cronquist1, J. McCollum1, R. Katz2, and I. Kleyner3 1Actel Corporation, Sunnyvale, CA94086 2NASA Goddard Space Flight Center, Greenbelt, MD20771 3Orbital Sciences Corporation, Greenbelt, MD20771

  2. Abstract The single event effects of a 0.15µm antifuse-based field programmable gate array (FPGA) are investigated by heavy-ion beam test and computer simulation. Single event upsets of user flip-flop, clock, control logic, and embedded SRAM are identified and mitigation methods are proposed.

  3. Motivation • To investigate the following subjects by heavy-ion-beam test and computer simulation • Harden the SEU of 0.15µm technology, million system gate AX1000 without architecture changes so that inexpensive commercial part can be used for prototyping • Implement harden by design (HBD) methodology so that the same commercial foundry (UMC) can be used for manufacturing • SEU hardened part–RTAXS tradeoffs • PLL will be dropped because the speed demand is not as high as commercial part (telecommunication applications) • SET in combinational logic is not considered in the hardening

  4. Device AX1000 Manufacturing Technology 0.15 µm CMOS, 7 Layers Metal Foundry UMC Substrate Bulk Silicon Power Supply (VCCI/VCCA) 2.5 V, 3.3 V/1.5 V Number of Antifuse Switches 29,000,000 Number of I/O Banks 8 Number of Logic Tiles 9 Number of Combinational Modules 12,096 Number of Flip-Flop Modules 6,048 Number of Embedded SRAM Bits 165,888 (9x18,432) Device Under Test

  5. PLL One SRAM Block One IO Bank One Core Tile Core Logic PLL Y = 11.5 mm X = 12.4 mm

  6. AX1000 Functional Blocks • Programming network for configuring antifuse switches • Control logic circuits for chip configuration during programming, testing, and operation • I/O blocks for flexible signal threshold, and high-speed low voltage differential signal (LVDS) interface • Clock network and flip-flop modules for logic implementation • Combinational and flip-flop modules for logic implementation • Embedded synchronized SRAM block for fast memory implementation

  7. Heavy Ion Beam Test • Logic Test • DUT has 4 FIFO shift register composed of user flip-flops, DOC and DOS has 100-bits each, SH1 and SH2 has 4-bits each • Dynamical signal pattern of ‘0’, ‘1’, or checkerboard is clock in the shifter registers at 1MHz • Power supply current was monitored in-flux to detect SEL and SEDR • SRAM Test • DUT uses one SRAM block configured 1x4096 • Statically compared pre-irradiation and post-irradiation bit maps • Nominal bias VCCI/VCCA = 3.3V/1.5V, room temperature • Facility • BNL Tandem Van de Graaf, Ions: C, F, Cl, Br, and I • No boneless duck

  8. Control Logic SEU • Recorded as CLU in Table II • SEU occurred in tile startup sequencer state machine, depends on which bit been upset • Input ‘0’ into each user flip-flop • Generate a runt clock pulse • Set flip-flop to ‘1’ • Reset flip-flop to ‘0’ • Affect every flip-flop in the same tile • SEU occurred in bank I/O startup sequencer state machine, depends on which bit been upset • Alter the I/O configuration (PCI, TTL, CMOS, etc.) • Input ‘0’ into input of the design • Tri-state output of the design • Affect every I/O in the same bank • Startup sequencer will be “fixed” in 20µs by automatic detection and repairing

  9. Control Logic SEU in Tile Startup Sequencer DATA Q D ISOIN User FF Q Q Q D D D START • • • TSSF1 TSSF2 TSSF5 Tile Startup Sequencer Logic schematic showing part of Startup Sequencer and its functionality. After startup, every sequencer flip-flop is set at state '1'. When the heavy ion irradiation upset the ISOIN flip-flop to '0', the data in the user flip-flop will be set to '0' at the next clock edge. Each logic tile has one sequencer, all the user flip-flop in the same tile will simultaneously have the same SEU effect. There are 5 bits in the tile startup sequencer, SEU in each bit has a particular effect.

  10. Sketch showing the behavior of clock SEU. When a shift register is clocked in checkerboard pattern, a clock SEU will cause a jump in the error counts of registers in DUT. The maximum jump is the bit-length of the register. Number of Errors Maximum jump equals to bit length Clock upset Run Time Clock SEU

  11. SEU in User Flip-Flop 10-4 10-5 10-6 10-7 10-8 10-9 10-10 Signal pattern is checkerboard. Short 1 and short 2 are 4-bits long FIFO shift registers, DOC and DOS are 100-bits long.

  12. SEU in User Flip-Flop 10-5 10-6 10-7 10-8 10-9 10-10 Signal pattern is ‘0’. Control logic upset contributes to data scattering.

  13. SEU in User Flip-Flop 10-6 10-7 10-8 10-9 10-10 Signal pattern is ‘1’. The scarcity of data due to control logic upset.

  14. SEU in Embedded SRAM 10-7 10-8 10-9 10-10 10-11 SRAM was tested statically. 8802 and 8803 are the serial number of two separate DUT.

  15. SEU in Embedded SRAM 00000000000000010000000010000000000000000000000100000000000000000000000100100000000000000000000000000000000000000000000000000000 00000100000000000000000000000000000000000010000000000000000000000010000000000000000000000000010000000000000000000000000000010000 00000000000100000000000000000000000000000000000000000100000000000010000000000000000000000000000000100000000000000000000010000000 00000000000000000000000000000000000000000000000000000000000001000000000000001000000000000000100000000000000000000000000000000000 00000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000001000100000000000000000000000000000000000000001000000000000000000 00000100000000000000100000000000001001000000000100000000010000001000000001000000000100000000000000000000000000100000000000000000 00000000000000000000000000000000000000000000000000000000100000000000000100000000000000000000000000000000000000001000000010000000 00000000000000010000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000001000000000000000 00000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001 00000001000000000001110000010000001000000000000000000000000000000010000000000000000000000000000000000000000000000000000010010000 00000000000000000001000000000000100000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000010000000000000000000000000 00000000000001000000000000010000000000000000010000000010100100000000000000000000000000000000000000000000000000000010000000000001 00000000000000000000000000000000000000000010000000000000000100000000100000000000000000000000000000000000000000000000000000000000 00000000000000000010000000000100000000000000000000000000000000001000001000000000000000000000000000000000000000100000000000000000 00000000000001010010000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000 00000000001000000000000000000000000000000000000000000000000100000000000000001000000000000000000000000000000000000000000100010010 00000001000000000000000000000000000000000000100000000001000000000000000000111000000000000000000000000000000000000000000010000000 00010000000000000000000100000000000000100000000100000001000000000000000000000000000000000000000000000000010000000000000000000000 00010000000000000000000000000000000000000000000000000000000000000000000000010000000000001000000000000000000000000000000000000000 00000001000000000000000000000100000000000000000000000000000110001001000000000000000000000000000000000000000000000000000000000001 00000000000000000000000000000000000000000000000000000000000000001001000000010000100000000000000000000000000000000000000000000000 01000000000000000000000000000000000000000000000000000000000000000000000001000000001000000001000000000000000000000000000000000001 00000000000000000000000000000000000100000000000010000000000000000000000000000000001000000000000000010000000000000000000000000000 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000 10000000000000000000000000100000000100100000000000001000000000000000000000000000000000000010000000000000000000000000000000000000 00000000000000000010011000010010000000000000010000000000000000000000000000001000000000000000000000000000000000000000000000010000 00000000000000000000001000000000010000000000010000000000000000000000000000000000000000001000000000001000000000000000010000000000 00000000000000000000100000000000000000010000000000000100000000000010000000000000000000000000000000000000000000000000000000001000 00000000000000000000000010000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000010000 00000000000000000000000000000000000000000000000100000000000000000000000000000010000110000000000100000000000000000000000000000000 Bit map showing the upset bits in red. The relative physical location of every bit is preserved in this map. Iodine ion tilt 45°, LET of 84.5 MeV•cm2/mg was used for irradiation. The upset clusters are multiple-bits upset.

  16. Heavy Ion Beam Test Data Table II Raw DATA Showing the Occurrence of Control Logic Upset (CLU)

  17. SEU Harden by Design • Control Logic • Logic redundancy design • Clock Network • Eliminate small leaves in the clock tree • Beef up the circuit • User flip-flop • Hard-wired triple redundant latch for master and slave • Embedded SRAM • EDAC macro in FPGA design software (ACTgen) • Hamming code detect two error bits, correct one error bit • Glancing-angle-strike double upset simulated by SPICE and SpaceRad to determine the bit separation • Charge-sharing double upset simulated by 3D mixed mode to determine the bit separation

  18. Triple Redundant Latch Logic schematic of the triple redundant latch in the SEU hardened user flip-flop.

  19. 3D Mixed Mode Simulation • To determine the design rules, the layout separation between two latches, for redundant hardenings in flip-flops and EDAC mitigation in SRAM (Hamming code for 2 error bits detection and 1 error bit correction) • Silvaco 3D Atlas • Models • SRH recombination • Auger generation • Fermi-Dirac statistics • Band-gap narrowing • Carrier-carrier scattering mobility modulation

  20. 3D Mixed Mode Simulation SRAM 1 SRAM 2 QB1 QB2 VCC VCC ‘1’= Q2 Q1 = ‘1’ P+ N+ N+ N+ N+ P+ 3D Device Structure Ion strike 0°-tilt at center of junction (Fig A) Ion strike 60°-tilt at center of structure (Fig B) Schematic showing the 3D device structure and SPICE circuit net. The device structure assumes the worst scenario, NMOSFET junction at high state is the sensitive area. Ion strikes at the sensitive junction of SRAM2 to simulate single-bit upset. Ion strikes at the center in all three directions of the structure to simulate double-bit upset.

  21. 3D Mixed Mode Simulation Sensitive junction (Q1) in SRAM1 Sensitive junction (Q2) in SRAM2 0.72 MeV-cm2/mg 0.77 MeV-cm2/mg 0.97 MeV-cm2/mg 10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 Fig A. 3D mixed mode simulation showing ion-strike-induced transient voltages of the sensitive junctions in SRAM1 and SRAM2. Three different LET heavy-ion-strikes were simulated. The heavy ion always strikes at the center of the sensitive junction of SRAM2. The threshold LET of a single upset in a SRAM-bit is determined as 0.77 MeV•cm2/mg.

  22. 3D Mixed Mode Simulation Sensitive junction (Q2) in SRAM2 Sensitive junction (Q1) in SRAM1 10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-710-610-5 Fig B. 3D mixed mode simulation showing ion-strike-induced transient voltages of the sensitive junctions in SRAM1 and SRAM2. Heavy ion with LET of 60 MeV•cm2/mg and 60° tilt strikes a location of equal distance to SRAM1 and SRAM2. The first voltage drop near 10 ps is due to the electric field collapsing. The main voltage drop near 10 ns is due to the charge collection of the diffused carriers at the sensitive junctions.

  23. Conclusions • No SEL for LET up to 120MeV-cm2/mg and no SEDR for normal incident LET up to 60MeV-cm2/mg. • The state-of-the-art high-gate-count antifuse-based FPGA can be hardened by design to meet the aerospace SEE requirement. • The main trade-off is speed. For moderate speed, such as 33 MHz PCI standard, the SEU hardening can be achieved by redundancy circuitry and feature size increase. • The penalty of die size increase can be alleviated by physical layout effort. • Complex sub-system and system abnormalities have to be studied diligently to interpret the beam test data. • Using both beam test and computer simulation as tools for proposing hardening methods offers high confidence level for meeting the product target.

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