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ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Dynamic Power: Device Sizing

ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Dynamic Power: Device Sizing. Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu

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ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Dynamic Power: Device Sizing

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  1. ELEC 5270/6270 Fall 2007Low-Power Design of Electronic CircuitsDynamic Power: Device Sizing Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html ELEC6270 Fall 07, Lecture 6

  2. Cg Delay of a CMOS Gate Intrinsic capacitance Gate capacitance CMOS gate Cint CL Propagation delay through the gate: tp = 0.69 Req(Cint + CL) ≈ 0.69 ReqCg(1 + CL /Cg), Cint≈ Cg = tp0(1 + CL/Cg) tp0 = intrinsic or unloaded delay ELEC6270 Fall 07, Lecture 6

  3. Req, Cg, Cint, andWidth Sizing • Sizing: Keep L fixed, increase W by size factor S • Req : equivalent resistance of “on” transistor for standard gate, proportional to L / W; reduces to Req / S • Cg : standard gate capacitance, proportional to CoxWL; increases to SCg • Cint : intrinsic output capacitance ≈ Cg, for submicron processes • tp0 : intrinsic delay = 0.69ReqCg; remains unchanged with sizing – is purely a function of the technology ELEC6270 Fall 07, Lecture 6

  4. Delay of a Gate Sized by Factor S tp = 0.69 Req/S (SCg + CL) = 0.69 ReqCg(1 + CL/SCg) = tp0 (1 + CL/SCg) Intrinsic delay of standard gate in technology Ratio of load capacitance to capacitance of sized gate ELEC6270 Fall 07, Lecture 6

  5. Effective Fan-out, F • Effective fan-out is defined as the ratio of the external load capacitance to the standard gate capacitance: F = CL/Cg tp = tp0(1 + CL/Cg) = tp0 (1 + F ) ELEC6270 Fall 07, Lecture 6

  6. Cg1 Cg2 Sizing an Inverter Chain #2 (size f2) #N (size fN) #1 (standard) CL Cg2 = f2Cg1 tp1 = tp0 (1 + Cg2 /Cg1) tp2 = tp0 (1 + Cg3 /Cg2) N N tp = Σtpj = tp0Σ (1 + Cgj+1/Cgj) j =1j=1 ELEC6270 Fall 07, Lecture 6

  7. Minimum Delay Sizing Equate partial derivatives of tp with respect to Cgj , j = 2, 3, . . ., to 0: 1/Cg1 – Cg3/Cg22 = 0, etc. or Cg22 = Cg1×Cg3, etc. or Cg2/Cg1 = Cg3/Cg2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: CL/Cg1 = F = f N, tp = Ntp0(1 + F1/N) ELEC6270 Fall 07, Lecture 6

  8. Minimum Delay Sizing Equate partial derivatives of tp with respect to N to 0: dNtp0(1 + F1/N) ───────── = 0 dN i.e. F1/N – F1/N(ln F)/N = 0 or ln f = 1 → f = e = 2.718 and N = ln F ELEC6270 Fall 07, Lecture 6

  9. Delays of Loaded Gates • F = fan-out factor • Single stage, no sizing tp = tp0 (1 + F) • Two-stage optimum sizing tp = 2tp0 (1 + √F) • N = ln F stage optimum sizing tp = tp0 ln F (1 + N√F) ELEC6270 Fall 07, Lecture 6

  10. Gate Delay Ratio of Intrinsic Delay J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, pp. 205-210. ELEC6270 Fall 07, Lecture 6

  11. Sizing for Energy Minimization Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, pp. 218-219. ELEC6270 Fall 07, Lecture 6

  12. CL Cg1 Sizing for Energy Minimization f 1 tp = tp0 [(1+f) + (1+F/f )] = tp0(2+ f + F/f ) F = CL/Cg1 tp0 ~ VDD/(VDD - Vth) Energy consumption, E=VDD2Cg1[1+(1+f)+(f+F)] =VDD2Cg1[2+2f+F] ELEC6270 Fall 07, Lecture 6

  13. Holding Delay Constant • Reference circuit: f = 1, supply voltage = Vref • Size the circuit such that the delay of the new circuit is smaller than or equal to the reference circuit: tp tp0(2+f+F/f ) VDD Vref -Vth 2+f+F/f ── = ──────── = ── ──── ───── ≤ 1 tpref tp0ref (3+F ) Vref VDD -Vth 3+F ELEC6270 Fall 07, Lecture 6

  14. Supply Voltage Vs. Sizing 3.5 3.0 2.5 2.0 1.5 1.0 F =1 Vref = 2.5V Vth= 0.5V 2 5 fopt ≈ √F VDD (volts) 10 1 2 3 4 5 6 f ELEC6270 Fall 07, Lecture 6

  15. Energy E VDD22 + 2f + F ── = ─── ────── Eref Vref2 4 + F ELEC6270 Fall 07, Lecture 6

  16. Normalized Energy Vs. Sizing 1.5 1.0 0.5 Vref = 2.5V Vt = 0.5V F =1 2 5 fopt≈ √F Normalized Energy 10 1 2 3 4 5 6 f ELEC6270 Fall 07, Lecture 6

  17. Summary • Device sizing combined with supply voltage reduction reduces energy consumption. • For large fan-out energy reduction by a factor of 10 is possible. • An exception is F = 1 case, where the minimum size device is also the most effective one. • Oversizing the devices increases energy consumption. ELEC6270 Fall 07, Lecture 6

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