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Pipelining Hazards

Prof. Sirer CS 316 Cornell University. Pipelining Hazards. Pipelining Recap. Powerful technique for masking latencies Logically, instructions execute one at a time Physically, instructions execute in parallel Decouples the processor model from the implementation

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Pipelining Hazards

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  1. Prof. Sirer CS 316 Cornell University Pipelining Hazards

  2. Pipelining Recap • Powerful technique for masking latencies • Logically, instructions execute one at a time • Physically, instructions execute in parallel • Decouples the processor model from the implementation • Interface vs. implementation • Dependencies between instructions complicate the implementation

  3. Hazards • Data hazards • A required operand is not ready • Usually because a previous instruction in the pipeline has not committed it to the register file yet • Control hazards • The next instruction to fetch cannot be determined • Usually because a jump or branch instruction has not determined the next PC yet • Structural hazards • Two instructions in the pipeline try to simultaneously access the same resource

  4. Data Hazards • Stall • Keep track of all instructions in the pipeline, and all registers they may affect • Detect that there will be a conflict • Inject NOPs (“bubbles”) into the pipeline until the hazard is gone • Data Forwarding • Keep track of all instructions in the pipeline, and all registers they may affect • Add additional circuitry and wires to route data from a later stage back to an earlier stage

  5. Control Hazards • Stall • Inject NOPs into the pipeline when the next instruction is not known • Pros: simple, clean; Cons: slow • Delay Slots • Tell the programmer that the N instructions after a jump will always be executed, no matter what the outcome of the branch • Pros: The compiler may be able to fill the slots with useful instructions; Cons: breaks abstraction boundary • Speculative Execution • Insert instructions into the pipeline • Replace instructions with NOPs if the branch comes out opposite of what the processor expected • Pros: Clean model, fast; Cons: complex

  6. Types of Hazards • RAW – Read After Write • WAR – Write After Read • WAW – Write After Write • RAW indicates data dependence • WAW and WAR hazards stem from register reuse • Exercised by out-of-order execution • Register renaming can eliminate them

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