Interrupts AXI GPIO and AXI Timer

ECE 699: Lecture 4 Interrupts AXI GPIO and AXI Timer

Required Reading The ZYNQ Book Tutorials • Tutorial 2: Next Steps in Zynq SoC Design ZYBO Reference Manual • Section 13: Basic I/O LogiCORE IP AXI GPIO Product Specification LogiCORE IP AXI GPIO v2.0 Product Guide LogiCORE IP AXI Timer v2.0 Product Guide Zynq-7000 All Programmable SoC – Technical Reference Manual • Chapter 7: Interrupts

Recommended Reading The ZYNQ Book • Chapter 10.4: Interrupts ARM Generic Interrupt Controller – Architecture Specification • Chapter 1: Introduction • Chapter 2: GIC Partitioning • Chapter 3: Interrupt Handling and Prioritization • Chapter 4: Programmers’ Model

ZYBO Board Source: ZYBO Reference Manual

ZYBO Board Components Source: ZYBO Reference Manual

Class Exercise 1: Modifying a Counter Using Pushbuttons

Class Exercise 2: Modifying a Counter Using AXI Timer (every N ms)

ZYBO General Purpose Input Output (GPIO) Source: ZYBO Reference Manual

AXI GPIO Core Connected to Buttons

AXI Timer Core Implemented in Programmable Logic

Mapping of an Embedded SoC Hardware Architecture to Zynq Source: Xilinx White Paper: Extensible Processing Platform

A Simplified Model of the Zynq Architecture Source: The Zynq Book

Block Design for Class Exercise 1 btns leds DDR FIXED_IO

Block Design for Class Exercise 2 leds btns DDR FIXED_IO

Block Diagram of AXI GPIO enabled only when the C_INTERRUPT_PRESENT generic set to 1 IPIC – IP Interconnect interface Source: LogiCORE IP AXI GPIO: Product Specification

Setting GPIO Core Parameters in Vivado 4

GPIO Core Source: LogiCORE IP AXI GPIO: Product Specification

AXI Interconnects and Interfaces Source: The Zynq Book

Constraints File

entity design_int_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; leds_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 ); btns_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); end design_int_wrapper;

design_1_i: component design_1 port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, leds_tri_o(3 downto 0) => leds_tri_o(3 downto 0), btns_tri_o(3 downto 0) => btns_tri_i(3 downto 0) );

ZYBO_Master.xdc (1) ##LEDs ##IO_L23P_T3_35 set_property PACKAGE_PIN M14 [get_ports {leds_tri_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[0]}] ##IO_L23N_T3_35 set_property PACKAGE_PIN M15 [get_ports {leds_tri_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[1]}] ##IO_0_35 set_property PACKAGE_PIN G14 [get_ports {leds_tri_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[2]}] ##IO_L3N_T0_DQS_AD1N_35 set_property PACKAGE_PIN D18 [get_ports {leds_tri_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[3]}]

ZYBO_Master.xdc (3) ##Buttons ##IO_L20N_T3_34 set_property PACKAGE_PIN R18[get_ports {btn_tri_i[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {btn_tri_i[0]}] ##IO_L24N_T3_34 set_property PACKAGE_PINP16[get_ports {btn_tri_i[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {btn_tri_i[1]}] ##IO_L18P_T2_34 set_property PACKAGE_PINV16[get_ports {btn_tri_i[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {btn_tri_i[2]}] ##IO_L7P_T1_34 set_property PACKAGE_PIN Y16[get_ports {btn_tri_i[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {btn_tri_i[3]}]

Interrupts

Global Interrupt Enable, GIER Source: LogiCORE IP AXI GPIO: Product Specification

Interrupt Enable Registers, IP IER Source: LogiCORE IP AXI GPIO: Product Specification

Interrupt Status Registers, IP ISR Status Status Source: LogiCORE IP AXI GPIO: Product Specification

Addresses of Interrupt-Related AXI GPIO Registers Source: LogiCORE IP AXI GPIO: Product Specification

AXI GPIO Resource Utilization and Maximum Clock Frequency Source: LogiCORE IP AXI GPIO: Product Specification

AXI Timer

Functions of a Typical Timer (1) Generating delays - imposing a specific delay between two points in the program label 1 instr1 instr2 delay instrN label2

Functions of a Typical Timer (2) 2. Output compare - generating signals with the given timing characteristics single pulse periodical signal pulse width period

Functions of a Typical Timer (3) 3. Input capture - measuring the time between signal edges start stop stop start

Block Diagram of AXI Timer Source: LogiCORE IP AXI Timer: Product Guide

AXI Timer: Modes of Operation • Generate Mode • Capture Mode • Pulse Width Modulation Mode • Cascade Mode

Generate Mode • Counter when enabled begins to count up or down • On transition of carry out, the counter • stops, or • automatically reloads the initial value from the load register,and continues counting • if enabled, GenerateOut is driven to 1 for one clock cycle • if enabled, the interrupt signal for the timer is driven to 1 • Can be used to • Generate repetitive interrupts • One-time pulses • Periodical signals

Capture Mode • The counter can be configured as an up or down counter • The value of the counter is stored in the load register when the external capture signal is asserted • The TINT flag is also set on detection of the capture event • The Auto Reload/Hold (ARHT) bit controls whether the capture value is overwritten with a new capture value before the previous TINT flag is cleared • Can be used to measure • Widths of non-periodical signals • Periods of periodical signals • Intervals between edges of two different signals, etc.

Pulse Width Modulation (PWM) Mode • Two timer/counters are used as a pair to produce an output signal (PWM0) with a specified frequency and duty factor • Timer 0 sets the period • Timer 1 sets the high time for the PWM0 output • Can be used to generate • Periodical signals with varying period and duty cycle

Cascade Mode • Two timer/counters are cascaded to operate as a single 64-bit counter/timer • The cascaded counter can work in both generate and capture modes • TCSR0 acts as the control and status register for the cascaded counter. TCSR1 is ignored in this mode. • Can be used to • Generate longer delays • Generate signals with larger pulse widths or periods • Measure longer time intervals

Timer/Counter Register, TCR0, TCR1 Source: LogiCORE IP AXI Timer: Product Guide

Load Register, TLR0, TLR1

Control/Status Registers, TCSR0 Source: LogiCORE IP AXI Timer: Product Guide

Control/Status Register 0, TCSR0

Control/Status Registers, TCSR0

Interrupts AXI GPIO and AXI Timer