Network on Chip - Architectures and Design Methodology

1. Network on Chip -Architecturesand Design Methodology Natt Thepayasuwan Rohit Pai

2. “By the end of the decade, SOCs using 50-nm transistors operating below one volt, will grow to 4 billion transistors running at 10GHz” -International Technology Roadmap for Semiconductors

3. Challenges in SOC design • Synchronization with single clock source and negligible skew will be extremely difficult, if not impossible. • Globally asynchronous – Locally synchronous • Distributed System on single chip • Global control of information traffic is unlikely to succeed. • Autonomous data transfers by components

4. Challenges (cont) • Electrical noise due to cross-talk, electro-magnetic interference (EMI) and radiation induced charge injection (soft errors) will be likely to produce data upsets. • The mere transmission of digital values on wires will be inherently unreliable.

5. Drawbacks of Bus • Every unit attached adds additional parasitic • Bus timing is difficult in deep sub micron process • Bus testability is problematic • Bus arbiter delay grows with number of masters • Bandwidth is limited and shared

6. Application System Transport Network Data link Physical The Network-on-Chip The seven layer OSI stack for communication ! Micro – Network Stack

7. Physical Layer • Lowest level • signal voltage, timing, bus widths and pulse shape • Power consumption difficult to compute at this stage • signal synchronization is a concern

8. Data Link • Reliable transfer of data • Error detection and correction • Arbitration of physical medium • MAC protocols – token ring and TDMA • Arbitration scheme affects delay, throughput, power consumption

9. Network Layer • Provides topology independent view of end to end communication to upper layers • Data routes can be persistent / each transaction can be dynamically routed • Congestion control may be required if dynamically routed

10. Transport Layer • End –to-end connection ! • Flow control, packet reassembly, re-ordering • Abstraction of network • Formal method of communication

11. System- Session & Presentation • Session • Adds state to end-to-end connections. • Synchronous messaging requires sending and receiving components rendezvous as message is passed • State maintained by a semaphore used as an indicator • System components are CPU, DSP core, memory …. • Presentation • Byte ordering format conversion

12. Application Layer • Highest layer of abstraction • eg: Embedded system performs video processing • Separation of computation and communication • Builds upon functionality of lower level

13. NOC Architectures Platform based design Same architecture for different application –speeds up design process and reduces verification time Issues- Generality / Performance

14. CLIQUE Architecture Chip level Integration of Communicating Heterogeneous Elements

15. Regions & Wrappers • Region : Area insulated from the network and has a different internal topology/ communication • Allows resources of larger size than atomic mesh • Connected to NOC by Wrappers, routes the packets to insulate from external traffic • Wrappers convert messages messages to appropriate formats

16. Backbone-Platform-System • Encapsulate design into reusable platforms • Backbone (Region Type) • Topological & communication issues • channels, switches & network interface • Performance evaluation of topologies • Customized (wire-length,timing,physical) topology enables NOC where QoS is optimized in the beginning

17. BPS (cont) • Platform (Region scaling) – Requires understanding of the functionality (System level control) • Complexity and performance requirements • Metrics – utilization,performance, capacity, temporal and spatial effects Processor Hardware Code Configuration CommunicationStructure

18. BPS (cont) • Application Development – (Resource level) • control of network • functionality of network

19. Switching Networks • Circuit Switching • Space switching- S (crossbar) • Time switching – T : buffer to swap order of time-slices on TDMA links • Adv: Formal guarantee of bandwidth • Disadv: Lack of reactivity against changing communcation • eg: not suited for random traffic b/w CPU and slaves

20. PROPHID (TST) S T T

21. Packet Switching • Routers as switching elements • Header + Payload = Packet • Routing decisions dynamic and distributed • Very reactive • What about latency?

22. Wormhole • Extensive use in in high performance parallel computing • Router does not wait for trailer Tail Head

23. SPIN • Scalable, Programmable, Integrated Network • 32 bit packets – header byte for destination address • 256 terminals addressed • Trailer has checksum for error detection • Payload should be large • Deterministic routing • Latency independent

24. FAT – Tree

25. Router Design • Area optimization (on-chip) • Packets queued in FIFO at input leads to max contention • Addition output buffers required • Contention in the child links than father links • Output buffers reduces cascaded contention

26. Beyond NOC • Currently used communication architectures on SoC • Priority Based Shared Static Bus • Time Division Multiplexing Access (TDMA) Shared Bus

27. Static Priority based shared Bus

28. TDMA

29. TDMA

30. Problems with both • Static Priority Based Shared Bus • lack of control over the allocation of communication bandwidth to different system components or data flows • TDMA Based Shared Bus • significant latencies resulting from variations in the time-profile of the communication requests

31. Lottery Bus

32. Operation The probability that bus is granted to Ci The probability that a task with t tickets can access the bus after n lottery drawings:

33. Hardware (static)

34. Hardware (dynamic)

35. Comparing BUS with NOC Bus says:Bus latency is zero once arbiter has granted control Noc says: Internal n/w causes small latency Bus says: Silicon cost of a bus is near zero NOC says: Significant silicon area Bus says: compatible with most Ips NOC says: IPs need smart wrappers NOC says: What do I do now?

36. Comparing NOC with BUS (cont)