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Silicon Tracking / Silicon Readout R&D. Richard Partridge SLAC / Brown. Overview. Silicon is the tracking technology best suited for the energy frontier Best resolution for high momentum Best 2-hit separation for tracking in the core of jets Best time resolution for resolving beam crossing
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Silicon Tracking / Silicon Readout R&D Richard Partridge SLAC / Brown SLAC Annual Program Review
Overview • Silicon is the tracking technology best suited for the energy frontier • Best resolution for high momentum • Best 2-hit separation for tracking in the core of jets • Best time resolution for resolving beam crossing • SLAC has initiated a number of R&D efforts aimed at improving upon the current state of the art • Low-mass silicon strip detectors with bump bonded readout • High density bump bonded readout chips (KPiX) • Construction of a silicon lab at SLAC • Development of simulation tools for silicon tracker optimization • R&D is motivated by interest in a “Silicon Detector” for a future linear collider • Outcome of the R&D likely to have broader range of application SLAC Annual Program Review
Low Mass Sensor Design • Present generation silicon trackers compromised by tracker material • R&D at SLAC focused on a drastic reduction in material in the context of precision physics at a linear collider • Low duty cycle allows air cooling • Readout chip bump bonded to sensor • Carbon fiber support cylinders SLAC Annual Program Review
Double Metal Sensor R&D • Double metal sensor design aimed at radically reducing tracker material • Readout chip is bump bonded directly to the strip sensor • Second sensor metal layer used to route strip signals to readout chip • Prototype sensors have been procured from Hamamatsu • 20 full size sensors (93 x 93 mm2) • 40 small test sensors • 40 “charge division” sensors to test measuring coordinate || to strip Photograph of prototype double metal sensor SLAC Annual Program Review
Double Metal Sensor Module • Each of the 1840 readout strips is routed to a bump bond pad for attachment to the KPiX readout chip • Power, ground, clock, and data signals are brought to the sensor on a kapton cable • Routing of signals between cable and readout chip is done using the double metal layer • Critical system tests of sensor + readout + cable planned for the coming year SLAC Annual Program Review
KPiX Readout Chip • KPiX developed by SLAC with unique capabilities: • Designed for high channel count (1024/die) with bump bonding • Pulsed power minimizes power dissipation at low duty cycle • Four time-stamped buffers per channel during acquisition, readout at low power between bunch trains SLAC Annual Program Review
0.25μm TSMC 32×32 array = 1024 channels Internal 13-bit ADC 4 Samples per train Automatic range switching Bias current for DC sensors Power down between trains Built-in calibration Nearest neighbor trigger High-gain feedback cap for tracker application Digital core with serial output External trigger for test beam Dual polarity for GEM / RPC KPiX64 single cell of KPiX 200 μm 500 μm KPiX Features SLAC Annual Program Review
KPIX Interface • Supports locally mounted KPIX for performance testing • KPIX show in copper container • Supports connection to external interface board • RPC interface board shown SLAC Annual Program Review
KPIX Data Acquisition • FPGA Control Board • USB Interface to PC • Future Upgrade To Ethernet • Interface To External Logic • Beam Line Triggers • Scintillator Triggers • Laser Triggers • Optically Isolated To KPIX Interface Board • C++ API Under Linux SLAC Annual Program Review
KPix Performance • Preliminary results meet expectations: for linearity, range switching, and noise • Next step is increasing channel count: 64 256 1024 SLAC Annual Program Review
Silicon Lab • SLAC is equipping a silicon lab to support broad range of silicon R&D efforts at SLAC • Facilities will include: • 500 ft2 clean room • Probe station in light box • Multi-sensor CMM • Laser test stand • Wire bonder • Glue station • Instrumentation (LCR, bias sources, etc.) • Lab space in building 84 has been cleared in preparation for clean room construction • Completion expected in FY09 SLAC Annual Program Review
Silicon Tracking Simulations • SLAC has been leading an effort to develop tracking simulation software expressly designed for the task of silicon tracker optimization • Simulation software goals: • Provide realistic simulations with full pattern recognition • Software must be sensitive to the tracker design details • Tracker geometry / configuration must be easy to change allowing rapid comparison of design alternatives • The tracking simulation infrastructure includes: • Flexible definition of detector geometry using xml text file • Detailed GEANT4-based modeling of detector response • Full simulation of charge collection in silicon strips and pixels • Robust track finding algorithms for pattern recognition studies SLAC Annual Program Review
Building a Virtual Tracker • Tracker geometry specified in an xml text file • Handles cylinders, disks, planar detectors, and polycones Example: Pinwheel outer barrel layer with full overlap in phi and z specified by the following xml code - <layer module="SiTrackerModule"> <barrel_envelope inner_r="1208.0" outer_r="1265.0“ z_length="3260.0" /> <rphi_layout phi_tilt="0.19" nphi="90" phi0="0.01745" rc="1228.0“ dr="0.0" /> <z_layout dr="5.5" z0="1581.0" nz="37" /> </layer> Additional xml lines describe the geometry of other layers and makeup of each module (layers of silicon, carbon fiber, kapton, epoxy, copper, rohacell foam, etc) SLAC Annual Program Review
100% |cos q | = 0.99 Efficiency Polar Angle SiD Baseline Tracker Design Track Reconstruction Software • New tracking SW developed expressly for design studies • Handles any combination of pixel, axial strip, or stereo strip layers in barrel or disk geometry • Pattern recognition is agnostic as to sensor type no coding of special cases for different combinations of sensor types • All decisions based on a global c2 no tuned parameters SLAC Annual Program Review
Tracking Simulations Status • Immediate goal is to optimize the SiD tracker design this summer in preparation for the SiD LOI • Also looking at simulating Atlas upgrade options to assist in the tracker upgrade design SLAC Annual Program Review
Summary • SLAC is engaged in an innovative silicon detector R&D program for next generation silicon trackers • R&D is motivated by the needs of a future linear collider, but the R&D is likely to have broader application to this key technology • Focus is on an innovative double metal sensor design that seeks to minimize tracker material and KPiX readout • Prototype sensors have been procured, KPiX64 is in hand, and a prototype cable is in the final design stage at U. New Mexico • System tests will be carried out during the coming year • A silicon lab is being equipped to support this program, as well as other silicon R&D taking place at SLAC • Tracking simulation software has been developed to assist in the optimization of silicon tracker designs SLAC Annual Program Review