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Search-Based Synthesis of Approximate Circuits Implemented into FPGAs

This paper introduces a systematic approach for optimizing circuits in LUT-based FPGAs by relaxing exactness requirements to improve performance and energy efficiency. The proposed method uses genetic programming to approximate circuits while satisfying given conditions, achieving significant reductions in error rates. Evaluation results showcase the effectiveness of the approach on various benchmark circuits. State-of-the-art synthesis tools fall short in comparison, highlighting the potential of the new method in FPGA design optimization.

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Search-Based Synthesis of Approximate Circuits Implemented into FPGAs

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  1. Search-BasedSynthesisof ApproximateCircuitsImplemented into FPGAs Zdeněk VAŠÍČEK, Lukáš SEKANINA Brno University of Technology, FacultyofInformation Technology Božetěchova1/2, 612 66 Brno - Královo Pole vasicek@fit.vutbr.cz

  2. Introduction • Approximatecomputingparadigm • The requirement of exact numerical or Boolean equivalence between the specification and implementation of a circuit is relaxed in order to achieve improvements in performance or energy efficiency [Venkatesan et al., 2011]. • The requirement of exactness can be relaxed because of: • limited perceptual capability of humans • a golden result is impossible (or difficult) to define • Our goal • To introduce a new systematic approach for theapproximation and optimization of circuits intended for LUT-basedFPGAs.

  3. Principle of the proposed approach • In order to deliver a good trade-off between the quality ofprocessing and implementation cost, ourmethod employs agenetic programming-based optimization engine. • The optimization engine applies various transformation rules on a given circuit and gradually modifies the circuit with aim to obtain its approximate version which satisfies a given condition (e.g. maximal error). candidate circuit 1 HD 81.25% | EP 13/16 candidate circuit 4HD 18.75% | EP 3/162 GATES original (accurate) circuit 5 GATES RESULT: error 18.8% reduction: 60% candidate circuit 3 HD 18.75% | EP 3/16 HD 0% | EP 0candidate circuit 2 GOAL: approx. ~ 20% error

  4. Results • The proposed method was evaluated on more than 40 circuits (24 included in the paper) taken from LGSynth, ITC and ISCAS benchmark sets. • Performance of five FPGA design tools was evaluated (four commonly available commercial and one state-of-the-art academia tool) • The current state-of-the-art synthesis tools provide(for some instances) the results that are far from an optimum (in average,16.3% reduction was achieved). For example, a 40% reduction (68 LUTs) was achieved for ‘clmb‘ benchmark circuit (Bus Interface) without introducing any error. • In average, 35.8% reduction can be obtained by introducing only a 0.2% error.

  5. Thankyouforyourattention!

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