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Synthesis of asynchronous circuits from petri nets

Synthesis of asynchronous circuits from petri nets. Delay models (I). A. C. B. Real (analog) behavior. Abstract behavior. A. B. C.

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Synthesis of asynchronous circuits from petri nets

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  1. Synthesis of asynchronous circuits from petri nets

  2. Delay models (I) A C B Real (analog) behavior Abstract behavior A B C Abstractions are necessary to define delay models manageable fordesign, synthesis and verification. Abstractions introduce optimisticand pessimistic simplifications that must be carefully taken into account.

  3. Delay models (II) • Separation between functionality and timing [Muller] • Every gate has a zero-delay atomic evaluator (Boolean function) • A delay is associated to every output (gate delay model)or every input (wire delay model) • Delays can be: • Unbounded (arbitrary finite delays) • Bounded (within given min/max bounds) Wire delay model Gate delay model

  4. Delay models (III) • Gate delay model: delays in gates, no delays in wires • Wire delay model: delays in gates and wires

  5. Delay models (IV) • Speed-independent circuit:hazard-free under the unbounded gate delay model • Delay-insensitive circuit:hazard-free under the unbounded wire delay model • Quasi-delay -insensitive circuit:delay-insensitive with some isochronic forks

  6. Speed-independent model • Pessimistic, since delays are typically bounded • Optimistic, since it assumes isochronic forks(negligible skew wrt the receiving gate delays) • Efficient synthesis methods exist Isochronic fork

  7. Fundamental mode of operation Inputs Outputs Circuit d d [Huffman 1964] : The circuit/environment interact with two phases (1) The environment sends inputs to the circuit (2) The circuit computes the outputs and the state signals The environment does not send new inputs until the circuit stabilizes Normal Fundamental Mode: Only one input changes at each communication cycle

  8. Input/Output mode of operation • Computation and communication can overlap (according to some specified protocol) • Event-based specification models are often used to describe the behavior (e.g., Petri nets). This tutorial will cover the synthesis of speed-independentcircuits that work under the I/O mode of operationand are specified using Petri nets.

  9. DI Delaymodelsforasync. circuits • Bounded delays (BD): realistic for gates and wires. • Technology mapping is easy, verification is difficult • Speed independent (SI): Unbounded (pessimistic) delays for gates and “negligible” (optimistic) delays for wires. • Technology mapping is more difficult, verification is easy • Delay insensitive (DI): Unbounded (pessimistic) delays for gates and wires. • DI class (built out of basic gates) is almost empty • Quasi-delay insensitive (QDI): Delay insensitive except for critical wire forks (isochronic forks). • In practice it is the same as speed independent BD SI  QDI

  10. Outline • Overview of the synthesis flow • Specification • State graph and next-state functions • State encoding • Implementability conditions • Speed-independent circuit • Complex gates • C-element architecture • Review of some advanced topics

  11. Book and synthesis tool • J. Cortadella, M. Kishinevsky, A. Kondratyev,L. Lavagno and A. Yakovlev,Logic synthesis for asynchronouscontrollers and interfaces,Springer-Verlag, 2002 • petrify:http://www.lsi.upc.es/petrify

  12. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  13. Specification x x y y z z z+ x- x+ y+ z- y- Signal Transition Graph (STG)

  14. x y z z+ x- x+ y+ z- y- Token flow

  15. xyz 000 x+ 100 y+ z+ z+ x- 110 101 x- x+ y+ z- y- y+ z+ 001 111 y- y+ x- 011 z- 010 State graph

  16. xyz 000 x+ 100 y+ z+ 110 101 x- y- y+ z+ 001 111 y+ x- 011 z- 010 Next-state functions

  17. Gate netlist x y z

  18. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  19. DSr LDS LDTACK D DTACK Read Cycle VME bus Bus Data Transceiver Device D DSr LDS VME Bus Controller DSw LDTACK DTACK

  20. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK

  21. LDTACK- DTACK- DTACK- LDTACK- LDS- LDS- Choice: Read and Write cycles DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ D+ LDTACK+ DTACK+ D- DSr- DTACK+ D- DSw-

  22. DTACK- DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles

  23. Circuitsynthesis • Goal: • Derive a hazard-free circuitunder a given delay model andmode of operation

  24. Speed independence • Delay model • Unbounded gate / environment delays • Certain wire delays shorter than certain paths in the circuit • Conditions for implementability: • Consistency • Complete State Coding • Persistency

  25. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  26. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK

  27. LDS + LDS = 0 LDS - LDS = 1 Binary encoding of signals DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- DTACK+ DSr-

  28. 01100 00110 Binary encoding of signals 10000 DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- 10010 LDS- LDS- LDS- LDTACK+ DSr+ DTACK- 10110 01110 10110 D+ D- DTACK+ DSr- (DSr , DTACK , LDTACK , LDS , D)

  29. ER (LDS+) LDS+ QR (LDS-) LDS- LDS- LDS- ER (LDS-) QR (LDS+) Excitation / QuiescentRegions

  30. LDS+ LDS- LDS- LDS- 10110 10110 Next-state function 0  1 0  0 1  1 1  0

  31. DTACK DSr DTACK DSr D LDTACK D LDTACK 00 00 01 01 11 11 10 10 00 00 01 01 11 11 10 10 Karnaugh map for LDS LDS = 1 LDS = 0 - - - 0 0 - 1 1 - - - - - - - - 1 1 1 - - - - - 0 0 - 0 0 0 - 0/1?

  32. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  33. DSr+ DSr+ DSr+ Concurrency reduction LDS+ LDS- LDS- LDS- 10110 10110

  34. Concurrency reduction DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS-

  35. State encoding conflicts LDS+ LDTACK- LDS- LDTACK+ 10110 10110

  36. CSC+ CSC- Signal Insertion LDS+ LDTACK- LDS- LDTACK+ 101101 101100 D- DSr-

  37. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  38. Complex-gate implementation

  39. Implementability conditions • Consistency • Rising and falling transitions of each signal alternate in any trace • Complete state coding (CSC) • Next-state functions correctly defined • Persistency • No event can be disabled by another event (unless they are both inputs)

  40. Implementability conditions • Consistency + CSC + persistency • There exists a speed-independent circuit that implements the behavior of the STG(under the assumption that ay Boolean function can be implemented with one complex gate)

  41. a- c+ a 100 000 001 b c b+ b+ Persistency a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay

  42. a+ 0000 a+ b+ 1000 b+ 1100 a- a- 0100 c+ c+ 0110 d+ d- d+ 0111 a+ a+ 1111 b- b- 1011 a- c- a- c- 0011 1001 a- c- d- 0001

  43. ab 0000 cd 00 01 11 10 a+ 1000 0 0 0 0 00 b+ 1100 1 0 a- 01 0100 c+ 1 1 1 1 0110 11 d- d+ 0111 1 10 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 ER(d+) ER(d-)

  44. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 ab cd 00 01 11 10 0 0 0 0 00 1 0 01 1 1 1 1 11 1 10 Complex gate

  45. S z C R Implementation with C elements • • •  S+  z+  S-  R+  z-  R-  • • • • S (set) and R (reset) must be mutually exclusive • S must cover ER(z+) and must not intersect ER(z-)  QR(z-) • R must cover ER(z-) and must not intersect ER(z+)  QR(z+)

  46. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 ab cd 00 01 11 10 0 0 0 0 00 1 0 01 1 1 1 1 11 1 10 S d C R

  47. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 but ... S d C R

  48. Assume that R=ac has an unbounded delay 0000 a+ 1000 b+ 1100 a- 0100 c+ R+ disabled (potential glitch) 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 Starting from state 0000 (R=1 and S=0): a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; S d C R

  49. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 S a- c- d 0011 1001 C R a- c- 0001 ab cd 00 01 11 10 0 0 0 0 00 1 0 01 1 1 1 1 11 1 10 Monotonic covers

  50. S d C R C-based implementations c d C b a c weak c d weak d a a b generalized C elements (gC)

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